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1. 发明专利

JP2005302736A Cord switch and pressure sensing device 审中-公开
标题翻译：齿轮开关和压力传感装置
公开(公告)号：JP2005302736A
公开(公告)日：2005-10-27
申请号：JP2005168092
申请日：2005-06-08
申请人： Asmo Co Ltd , Hitachi Cable Ltd , アスモ株式会社 , 日立電線株式会社
发明人： KASHIWAZAKI SHIGERU , YAGYU HIDEKI , HORII KOJI , ISHIHARA SHUSUKE , KIKUTA TOMOYUKI , TANAKA TAKESHI
IPC分类号： H01H13/18
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable cord switch and a pressure sensing device having a sensing region extended to the tip of the cord switch that can surely capture the on/off-action, and an error action is eliminated therefrom by allowing no contact between electrodes caused by bending, and having accurate detection ability for pressure from every direction.
SOLUTION: The cord switch 1 has at least two electric wires 2 each having a circular cross section in which each wires has an electrical conductive rubber layer or an electrical conductive plastic layer formed on the outer periphery of the metal conductive wire. The wires are arranged spirally in the length direction along the inner face of a hollow insulator 3 having a circular cross section, and the hollow insulator comprises restoring rubber or restoring plastic in a state that they are not mutually contacted each other and is fixed to the insulator 3 in a state of protruding toward the inside.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供高度可靠的线开关和压力感测装置，其具有延伸到帘线开关的尖端的感测区域，其可以可靠地捕获开/关动作，并且从其中消除误差动作通过弯曲导致电极之间不接触，并且具有来自各个方向的压力的精确检测能力。解决方案：电缆开关1具有至少两个电线2，每个电线2具有圆形横截面，其中每个电线具有形成在金属导线的外周上的导电橡胶层或导电塑料层。电线沿着具有圆形截面的中空绝缘体3的内表面在长度方向上螺旋地设置，并且中空绝缘体包括在彼此不相互接触的状态下恢复橡胶或恢复塑料，并固定到绝缘体3处于向内突出的状态。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2012235131A Nitride semiconductor epitaxial wafer for field effect transistor, nitride semiconductor-based field effect transistor, and method of manufacturing nitride semiconductor epitaxial wafer for field effect transistor 有权
标题翻译：用于场效应晶体管，氮化物半导体的场效应晶体管的氮化物半导体外延晶体及其制造用于场效应晶体管的氮化物半导体外延晶体的方法
公开(公告)号：JP2012235131A
公开(公告)日：2012-11-29
申请号：JP2012135361
申请日：2012-06-15
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： TANAKA TAKESHI , MATSUDA MICHIKO
IPC分类号： H01L21/205 , C23C16/34 , H01L21/20 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a nitride semiconductor epitaxial wafer that can relieve a trapping phenomenon of electrons and can suppress generation of a hexagonal defect.SOLUTION: In the method of manufacturing a nitride semiconductor epitaxial wafer 10 including forming a kernel generation layer 2 on a substrate 1, forming a first nitride semiconductor layer 3 on the kernel generation layer 2, and forming a second nitride semiconductor layer 4 having smaller electron affinity than the first nitride semiconductor layer 3 on the first nitride semiconductor layer 3, growth temperature when the first nitride semiconductor layer 3 is formed is made lower than that when the second nitride semiconductor layer 4 is formed.
摘要翻译：要解决的问题：提供一种可以减轻电子捕获现象并能够抑制六方缺陷的产生的氮化物半导体外延晶片的制造方法。解决方案：在包括在基板1上形成核生成层2的氮化物半导体外延晶片10的制造方法中，在核生成层2上形成第一氮化物半导体层3，形成第二氮化物半导体层4 比第一氮化物半导体层3上的第一氮化物半导体层3具有更小的电子亲和力，使得当形成第一氮化物半导体层3时的生长温度低于形成第二氮化物半导体层4时的生长温度。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2011199222A Nitride semiconductor epitaxial wafer, method of manufacturing the same, and field effect transistor element 有权
标题翻译：氮化物半导体外延晶体管，其制造方法和场效应晶体管元件
公开(公告)号：JP2011199222A
公开(公告)日：2011-10-06
申请号：JP2010067342
申请日：2010-03-24
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： TANAKA TAKESHI , NARITA YOSHINOBU
IPC分类号： H01L21/205 , C23C16/34 , C30B29/38 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a nitride semiconductor epitaxial wafer that has a higher breakdown voltage and reduces or eliminates a current collapse phenomenon, a method of manufacturing the same, and a field effect transistor element.SOLUTION: The nitride semiconductor epitaxial wafer includes a substrate 1, a first nitride semiconductor layer 3 formed on the substrate 1, and a second nitride semiconductor layer 5 formed on the first nitride semiconductor layer 3 and having smaller electron affinity than the first nitride semiconductor layer 3. The first nitride semiconductor layer 3 is doped with iron in a depth direction from a surface thereof with a depth-directional profile represented by an approximation expression of NFe=A×exp(B×C), (NFe: an iron concentration in the nitride semiconductor layer, A: 1E14 to 1E17 [cm], B: 3 to 8 [cm], C: a depth from the surface of the first nitride semiconductor layer), and a silicon doping region 4 formed by doping with silicon to a concentration higher than that of the iron is provided on the surface side of the first nitride semiconductor layer.
摘要翻译：要解决的问题：提供具有较高击穿电压并减少或消除电流塌陷现象的氮化物半导体外延晶片，其制造方法和场效应晶体管元件。解决方案：氮化物半导体外延晶片包括基板1，形成在基板1上的第一氮化物半导体层3和形成在第一氮化物半导体层3上并且具有比第一氮化物半导体层3小的电子亲和力的第二氮化物半导体层5.第一氮化物半导体层3 在其深度方向上用铁掺杂，具有由NFe = A×exp（B×C）的近似表达式表示的深度方向分布，（NFe：氮化物半导体层中的铁浓度，A：1E14至 1E17 [cm]，B：3〜8 [cm]，C：与第一氮化物半导体层的表面的深度）以及通过将硅掺杂到凹部而形成的硅掺杂区域4 在第一氮化物半导体层的表面侧设置比铁高的铁素体。

4. 发明专利

JP2010182943A Method of manufacturing nitride semiconductor epitaxial wafer 有权
标题翻译：制备氮化物半导体外延晶体的方法
公开(公告)号：JP2010182943A
公开(公告)日：2010-08-19
申请号：JP2009026351
申请日：2009-02-06
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： TANAKA TAKESHI , MATSUDA MICHIKO
IPC分类号： H01L21/205 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a nitride semiconductor epitaxial wafer that can relieve a trapping phenomenon of electrons and can suppress generation of a hexagonal defect. SOLUTION: In the method of manufacturing the nitride semiconductor epitaxial wafer 10 including forming a kernel generation layer 2 on a substrate 1, forming a first nitride semiconductor layer 3 on the kernel generation layer 2, and forming a second nitride semiconductor layer 4 having smaller electron affinity than the first nitride semiconductor layer 3 on the first nitride semiconductor layer 3, growth temperature when the first nitride semiconductor layer 3 is formed is made lower than that when the second nitride semiconductor layer 4 is formed. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以减轻电子捕获现象并能够抑制六方缺陷的产生的氮化物半导体外延晶片的制造方法。解决方案：在包括在基板1上形成核生成层2的氮化物半导体外延晶片10的制造方法中，在核生成层2上形成第一氮化物半导体层3，形成第二氮化物半导体层4 比第一氮化物半导体层3上的第一氮化物半导体层3具有更小的电子亲和力，使得当形成第一氮化物半导体层3时的生长温度低于形成第二氮化物半导体层4时的生长温度。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2006210660A Manufacturing method of semiconductor substrate 审中-公开
标题翻译：半导体衬底的制造方法
公开(公告)号：JP2006210660A
公开(公告)日：2006-08-10
申请号：JP2005020950
申请日：2005-01-28
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： TANAKA TAKESHI
IPC分类号： H01L21/265 , H01L21/02 , H01L33/06 , H01L33/32
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor substrate so as to form a nitride semiconductor film in a silicon substrate and the like. SOLUTION: The manufacturing method comprises a process for implanting ions in the vicinity of the surface of a first nitride semiconductor substrate 11, a process for overlaying the surface side of the first nitride semiconductor substrate 11 on a second substrate 2, a process for heat-processing the two overlaid substrates 11 and 2, and a process for exfoliating the greater part of first the nitride semiconductor substrate 11 from the second substrate 2 delimiting a layer 12 (13) in which the ion implantation is carried out. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供半导体衬底的制造方法以在硅衬底等中形成氮化物半导体膜。解决方案：制造方法包括在第一氮化物半导体衬底11的表面附近注入离子的工序，将第一氮化物半导体衬底11的表面侧覆盖在第二衬底2上的工序，工序用于对两个重叠的基板11和2进行热处理，以及从限定进行离子注入的层12（13）的第二基板2剥离第一氮化物半导体基板11的大部分的工序。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2013175696A Nitride semiconductor epitaxial wafer and nitride field effect transistor 有权
标题翻译：氮化物半导体外延晶体和氮化物场效应晶体管
公开(公告)号：JP2013175696A
公开(公告)日：2013-09-05
申请号：JP2012078469
申请日：2012-03-30
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： TANAKA TAKESHI , KANEDA NAOKI , NARITA YOSHINOBU
IPC分类号： H01L21/338 , C23C16/34 , H01L21/205 , H01L29/778 , H01L29/812
CPC分类号： H01L29/2003 , H01L21/0237 , H01L21/02378 , H01L21/02458 , H01L21/02494 , H01L21/02502 , H01L21/0254 , H01L21/0259 , H01L21/0262 , H01L29/04 , H01L29/1608 , H01L29/7786
摘要： PROBLEM TO BE SOLVED: To provide a nitride semiconductor epitaxial wafer and a nitride field effect transistor, which can inhibit current collapse.SOLUTION: A nitride semiconductor epitaxial wafer 200 comprises: an SiC substrate 101; a GaN layer 103 formed on the SiC substrate 101; and an AlGaN layer 104 formed on the GaN layer 103. The GaN layer 103 has a Wurtzite crystal structure. A ratio c/a between a grating constant c of the GaN layer 103 in a c-axis direction and a grating constant a of the GaN layer 103 in an a-axis direction is 1.6266 and under.
摘要翻译：要解决的问题：提供可以抑制电流崩溃的氮化物半导体外延晶片和氮化物场效应晶体管。解决方案：氮化物半导体外延晶片200包括：SiC衬底101; 形成在SiC衬底101上的GaN层103; 以及形成在GaN层103上的AlGaN层104. GaN层103具有纤锌矿晶体结构。在c轴方向上GaN层103的光栅常数c与GaN层103的a轴方向的光栅常数a之比c / a为1.6266以下。

7. 发明专利

JP2011035065A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011035065A
公开(公告)日：2011-02-17
申请号：JP2009178143
申请日：2009-07-30
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： TANAKA TAKESHI , MATSUDA MICHIKO
IPC分类号： H01L29/812 , H01L21/205 , H01L21/338 , H01L29/778
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving drain withstand voltage and suppressing inter-element leak current. SOLUTION: In this semiconductor device 1 formed by including, as constituent materials, a substrate 2, a first nitride semiconductor layer 4 formed on the substrate 2, a second nitride semiconductor layer 5 formed on the first nitride semiconductor layer 4 and having electron affinity smaller than that of the first nitride semiconductor layer 4; a source electrode 7 and a drain electrode 8 formed on the second nitride semiconductor layer 5 directly or through an intermediate layer 6 and arranged separately from each other; and a gate electrode 9 formed on the second nitride semiconductor layer 5 directly or through the intermediate layer 6 and arranged between the source electrode 7 and the drain electrode 8, carbon concentration in the first nitride semiconductor device 4 is lowered from the substrate 2 side to the second nitride semiconductor layer 5 side with respect to the depth (thickness) direction. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供能够提高漏极耐受电压并抑制元件间漏电流的半导体器件。解决方案：在该半导体器件1中，通过将基板2，形成在基板2上的第一氮化物半导体层4，形成在第一氮化物半导体层4上的第二氮化物半导体层5作为构成材料，电子亲和力小于第一氮化物半导体层4的亲和力; 形成在第二氮化物半导体层5上的源电极7和漏电极8直接或通过中间层6彼此分开设置; 以及形成在第二氮化物半导体层5上的直接或贯穿中间层6并设置在源电极7和漏电极8之间的栅电极9，第一氮化物半导体器件4中的碳浓度从衬底2侧降低到相对于深度（厚度）方向的第二氮化物半导体层5侧。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2010062443A Method of manufacturing compound semiconductor epitaxial wafer 有权
标题翻译：制备化合物半导体外延波长的方法
公开(公告)号：JP2010062443A
公开(公告)日：2010-03-18
申请号：JP2008228423
申请日：2008-09-05
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： MATSUDA MICHIKO , TANAKA TAKESHI
IPC分类号： H01L21/205
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a compound semiconductor epitaxial wafer capable of reducing a variation of a crystal growth distribution in a wafer surface by setting an optimal growth temperature of a nucleation layer with respect to the warpage of an individual single-crystal substrate.
SOLUTION: In this method of manufacturing the compound semiconductor epitaxial wafer 10, a nucleation layer 2 is formed on a single-crystal substrate 1 formed of a plurality of elements, and a plurality of nitride semiconductor layers 3 are formed on the nucleation layer. In the method, warpage α (μm) of the single-crystal substrate 1 is measured before forming the nucleation layer 2, and a growth temperature T (°C) in forming the nucleation layer 2 is set to satisfy T
摘要翻译：要解决的问题：提供一种制造化合物半导体外延晶片的方法，该化合物半导体外延晶片能够通过将成核层的最佳生长温度相对于翘曲的翘曲设定来减小晶片表面的晶体生长分布的变化单个单晶基板。解决方案：在这种制造化合物半导体外延晶片10的方法中，在由多个元件形成的单晶衬底1上形成成核层2，并且在成核上形成多个氮化物半导体层3 层。在该方法中，在形成成核层2之前测量单晶衬底1的翘曲α（μm），并且在形成成核层2时的生长温度T（℃）设定为满足T <4α+ 1,180，其中相对于单晶衬底1的翘曲α（μm）。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2006114653A Semiconductor epitaxial wafer and field-effect transistor 审中-公开
标题翻译：半导体外延晶体管和场效应晶体管
公开(公告)号：JP2006114653A
公开(公告)日：2006-04-27
申请号：JP2004299822
申请日：2004-10-14
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： TAKANO KAZUTO , TANAKA TAKESHI , KOUJI YOSHIHARU
IPC分类号： H01L29/812 , H01L21/338 , H01L29/778
摘要： PROBLEM TO BE SOLVED: To prevent a highly conductive region (conductive layer) from forming in a buffer layer with conductive impurities mixing into an epitaxial layer when preparing an electronic device such as a field-effect transistor containing a high electric mobility transistor or a hetero junction bipolar transistor on a semiconductor epitaxial wafer, and as a result to provide the semiconductor epitaxial wafer realizing high characteristics.
SOLUTION: The semiconductor epitaxial wafer having the buffer layer 2 on a substrate 1 has the buffer layer 2 forming an InAlN buffer layer 21 and an AlN buffer 22 sequentially.
COPYRIGHT: (C)2006,JPO&NCIPI

10. 发明专利

JP2006114652A Semiconductor epitaxial wafer and field effect transistor 审中-公开
标题翻译：半导体外延晶体和场效应晶体管
公开(公告)号：JP2006114652A
公开(公告)日：2006-04-27
申请号：JP2004299821
申请日：2004-10-14
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： KOUJI YOSHIHARU , TANAKA TAKESHI
IPC分类号： H01L29/812 , H01L21/205 , H01L21/338 , H01L29/778
CPC分类号： H01L29/7783 , H01L21/02378 , H01L21/0242 , H01L21/02458 , H01L21/02502 , H01L21/02505 , H01L21/0254 , H01L29/2003 , H01L29/66462
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor epitaxial wafer for realizing improved characteristics by preventing a highly conductive part (conductive layer) from being formed in a buffer layer due to the mixture of conductive impurities in the epitaxial layer, when manufacturing an electronic device, such as a field effect transistor and a hetero junction bipolar transistor including a high electron mobility transistor, on the semiconductor epitaxial wafer.
SOLUTION: In the semiconductor epitaxial wafer 2 having the buffer layer 2 on a substrate 1, the buffer layer 2 forms an AlN buffer layer 22 and a GaN buffer layer 21 successively.
COPYRIGHT: (C)2006,JPO&NCIPI

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