专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2014041879A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014041879A
公开(公告)日：2014-03-06
申请号：JP2012182632
申请日：2012-08-21
申请人： Toshiba Corp , 株式会社東芝
发明人： UCHIDA KENGO , AZUMA KAZUYUKI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446 , H01L2223/5448 , H01L2224/13025 , H01L2224/14181 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a structure for inhibiting the occurrence of a notch in a through silicon structure having a cross-section area larger than that of a TSV (Through Silicon Via) at the time of processing a through hole and for preventing leakage of metal when forming a semiconductor device having the TSV and the through structure having the cross-section area larger than that of the TSV; and provide a manufacturing method of the structure.SOLUTION: A semiconductor device comprises: first and second through holes 16, 17 which pierce a semiconductor substrate (silicon substrate 10) on which an element part Ra is formed from a rear face 10a side of an element formation surface 10b to the element formation surface 10b; and a circumferential insulation film 12 formed on a side wall of a bottom of the second through hole 17 in such a manner as to surround a circumference of the second through hole 17 having a larger opening size among the through holes.
摘要翻译：要解决的问题：提供一种结构，用于在加工通孔时防止在具有大于TSV（通过硅通孔）的截面面积的截面面积的贯通硅结构中产生凹口，并防止泄漏当形成具有TSV且贯穿结构的半导体器件的横截面面积大于TSV的半导体器件时; 并提供一种结构的制造方法。解决方案：一种半导体器件包括：第一和第二通孔16,17，其穿过其上形成有元件部分Ra的半导体衬底（硅衬底10），第一和第二通孔16,17由元件形成表面10b到元件形成表面10b; 以及周向绝缘膜12，其形成在第二通孔17的底部的侧壁上，以便围绕通孔中具有较大开口尺寸的第二通孔17的周边。

2. 发明专利

JP2011151316A Nonvolatile semiconductor memory device and method for manufacturing same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2011151316A
公开(公告)日：2011-08-04
申请号：JP2010013372
申请日：2010-01-25
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUDA TORU , AZUMA KAZUYUKI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66833 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device and a method for manufacturing the same which facilitates size reduction. SOLUTION: A stacked body is formed on a substrate by alternately stacking a doped semiconductor film and a non-doped semiconductor film, and a via-hole and a slit are formed in a first region. Then, by etching through the via-hole or the slit, a part of the non-doped semiconductor film arranged in the first region is removed, and a part arranged in the second region is left. Subsequently, an insulating material is embedded in a space formed by removing the non-doped semiconductor film. Subsequently, a charge storage film is formed on an inner surface of the via-hole, and a semiconductor pillar is formed in the via-hole. Further subsequently, in the second region, a contact hole piercing the stacked body is formed, a spacer insulating film is formed at a side thereof, and a contact is formed therein. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种有利于尺寸减小的非易失性半导体存储器件及其制造方法。解决方案：通过交替堆叠掺杂半导体膜和非掺杂半导体膜，在衬底上形成层叠体，并且在第一区域中形成通孔和狭缝。然后，通过蚀刻穿过通孔或狭缝，去除布置在第一区域中的部分非掺杂半导体膜，并且留下布置在第二区域中的部分。随后，绝缘材料嵌入在通过去除非掺杂半导体膜形成的空间中。随后，在通孔的内表面上形成电荷存储膜，并且在通孔中形成半导体柱。此外，在第二区域中，形成穿过层叠体的接触孔，在其一侧形成间隔绝缘膜，并在其中形成接触。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2011142276A Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2011142276A
公开(公告)日：2011-07-21
申请号：JP2010003307
申请日：2010-01-08
申请人： Toshiba Corp , 株式会社東芝
发明人： UENAKA TSUNEO , AZUMA KAZUYUKI
IPC分类号： H01L21/8247 , H01L27/00 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11578 , H01L27/105 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of executing a stable operation, and a method of manufacturing the same.
SOLUTION: A memory string MS includes a memory columnar semiconductor layer 36, a charge storage layer which includes a memory gate insulating layer 35 formed to surround a side surface of the memory columnar semiconductor layer 36, four-word line conductive layers 31a-31d formed to surround the memory gate insulating layer 35, and two protection layers 33a, 33b protecting upper parts of the word line conductive layers 30a-30d. The word line conductive layers 31a-31d constitute a stepped part ST formed stepwise so that positions of their ends are different from one another. An upper surface of a second step ST2 viewed from below is covered with the two protection layers 33a, 33b and an upper surface of a first step ST1 viewed from below is covered with one protection layer 33a.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够执行稳定操作的非易失性半导体存储器件及其制造方法。存储器串MS包括存储器柱状半导体层36，电荷存储层，其包括形成为围绕存储器柱状半导体层36的侧表面的存储栅绝缘层35，四字线导电层31a -31d形成为围绕存储栅极绝缘层35，以及两个保护层33a，33b，保护字线导电层30a-30d的上部。字线导电层31a-31d构成阶梯形部分ST，其阶梯状形成为它们的端部的位置彼此不同。从下方观察的第二步骤ST2的上表面被两个保护层33a，33b覆盖，从下方观察的第一台阶ST1的上表面被一个保护层33a覆盖。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2009253052A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009253052A
公开(公告)日：2009-10-29
申请号：JP2008099723
申请日：2008-04-07
申请人： Toshiba Corp , 株式会社東芝
发明人： AZUMA KAZUYUKI , WADA MAKOTO
IPC分类号： H01L21/768 , H01L21/3065 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a Via pattern that suppresses insulation breakdown caused by concentration of electric field in a convex portion of a contact plug.
SOLUTION: The present invention relates to a semiconductor device including: an interlayer insulating film 3 formed on a first wiring layer 1 and a first insulating layer 2; a connecting hole 4 formed inside the interlayer insulating film 3 so as to enlarge a cross-sectional shape gradually upward from a connecting part with the first wiring layer 1; a spacer film 5 continuously formed all over a side wall of the connecting hole 4 so as to enlarge a film thickness gradually upward from a predetermined depth; a contact plug 7 electrically connected with the first wiring layer 1 inside the spacer film 5; a second wiring layers 8 formed on the contact plug 7 and electrically connected with the contact plug; and a second insulating layer 9.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种包括Via图案的半导体器件，其抑制由接触插塞的凸部中的电场浓度引起的绝缘击穿。解决方案：本发明涉及一种半导体器件，包括：形成在第一布线层1和第一绝缘层2上的层间绝缘膜3; 形成在层间绝缘膜3内部的连接孔4，以从与第一布线层1的连接部分逐渐向上扩大横截面形状; 连续地形成在连接孔4的侧壁上的间隔膜5，从而使膜厚度从预定深度逐渐上升; 与间隔膜5内的第一布线层1电连接的接触插塞7; 形成在接触插塞7上并与接触插塞电连接的第二布线层8; 和第二绝缘层9.版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009182181A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009182181A
公开(公告)日：2009-08-13
申请号：JP2008020373
申请日：2008-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： WADA MAKOTO , KAJITA AKIHIRO , AZUMA KAZUYUKI
IPC分类号： H01L21/768 , H01L21/3065
CPC分类号： H01L21/76802 , H01L21/76816 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a wiring structure having high withstand voltage characteristics and leakage resistance characteristics, and a method for manufacturing the same. SOLUTION: The semiconductor device includes: a semiconductor substrate provided with semiconductor elements; contact members formed on the semiconductor substrate and electrically contacted with conductive members of an upper and lower layers; a first insulating film formed in the same layer as the contact members; a wiring located above a first region contacting with a part of an upper surface of the contact members and the first region, and including a second region wider than the first region; and a second insulating film formed above the first insulating film so as to contact with at least a part from an upper side of a side of the first region of the wiring and a bottom surface of the second region. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有耐高压特性和耐漏电特性的布线结构的半导体器件及其制造方法。解决方案：半导体器件包括：设置有半导体元件的半导体衬底; 接触构件形成在半导体衬底上并与上层和下层的导电构件电接触; 形成在与所述接触构件相同的层中的第一绝缘膜; 位于与接触构件的上表面的一部分和第一区域接触的第一区域上方的布线，并且包括比第一区域宽的第二区域; 以及第二绝缘膜，形成在所述第一绝缘膜的上方，以与所述布线的所述第一区域的一侧的上侧和所述第二区域的底面的至少一部分接触。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2009054941A Semiconductor device and semiconductor memory 有权
标题翻译：半导体器件和半导体存储器
公开(公告)号：JP2009054941A
公开(公告)日：2009-03-12
申请号：JP2007222600
申请日：2007-08-29
申请人： Toshiba Corp , 株式会社東芝
发明人： UCHIDA KANAE , ENDO MASATO , AZUMA KAZUYUKI
IPC分类号： H01L21/8247 , H01L21/3205 , H01L23/52 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/76802 , H01L21/76829 , H01L21/76832 , H01L21/76885 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor memory, which improve operation reliability.
SOLUTION: The semiconductor memory device includes: a memory cell transistor MT; a selection transistor whose source is connected to the drain of the memory cell transistor MT; an interlayer dielectric 51 for covering them; an insulating film 7 using the material of a dielectric constant higher than that of the interlayer dielectric 51; a contact plug 3 electrically connected to the drain of the selection transistor; and a bit line 2 in contact with the contact plug 3. Part of the bottom surface of the bit line 2 is positioned lower than the upper surface of the contact plug 3 and is positioned at the same height as the surface of the insulating film 7 or higher than the surface of the insulating film 7, and part of the bottom side is brought into contact with the side face of the contact plug 3.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供提高操作可靠性的半导体器件和半导体存储器。解决方案：半导体存储器件包括：存储单元晶体管MT; 源极连接到存储单元晶体管MT的漏极的选择晶体管; 用于覆盖它们的层间电介质51; 使用介电常数高于层间电介质51的材料的绝缘膜7; 电连接到选择晶体管的漏极的接触插塞3; 以及与接触插塞3接触的位线2.位线2的底面的一部分位于比接触插塞3的上表面低的位置，并且位于与绝缘膜7的表面相同的高度或高于绝缘膜7的表面，并且底侧的一部分与接触插塞3的侧面接触。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2006013229A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006013229A
公开(公告)日：2006-01-12
申请号：JP2004189929
申请日：2004-06-28
申请人： Toshiba Corp , 株式会社東芝
发明人： AZUMA KAZUYUKI , MATSUNAGA NORIAKI
IPC分类号： H01L21/288 , C25D7/12 , H01L21/3205 , H01L21/46 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/532 , H01L23/58 , H01L27/04
CPC分类号： H01L21/76877 , H01L21/2885 , H01L21/7684 , H01L23/53238 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve the inter-wafer face uniformity of plating film thickness.
SOLUTION: This semiconductor device with a semiconductor integrated circuit having a multi-layer wiring structure using metal wiring formed therein is provided with a plurality of chip regions 11 which are respectively formed as independent chips, and a plurality of chip rings 12 having a multi-layer wiring structure using metal wiring by which those chip regions are respectively surrounded. Those chip rings 12 are electrically connected.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提高电镀膜厚度的晶片间面均匀性。解决方案：具有使用在其中形成的金属布线的多层布线结构的半导体集成电路的该半导体器件设置有分别形成为独立芯片的多个芯片区域11和具有多个芯片环12的多个芯片环12，使用这些芯片区域分别围绕的金属布线的多层布线结构。那些芯片环12电连接。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005136335A Semiconductor device and method for manufacturing same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005136335A
公开(公告)日：2005-05-26
申请号：JP2003372989
申请日：2003-10-31
申请人： Toshiba Corp , 株式会社東芝
发明人： AZUMA KAZUYUKI , MATSUNAGA NORIAKI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532
CPC分类号： H01L21/76844 , H01L21/76874 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a via comprised of copper and having high SM tolerance. SOLUTION: The semiconductor device comprises an active element structure 2 which is formed on a semiconductor substrate 1 and has a connecting region 3 formed on the surface of the semiconductor substrate 1. A first insulating film 11 is disposed above the semiconductor substrate 1. A first wiring layer 12 made of copper is disposed on the surface of the first insulating film 11. A second insulating film 21 is disposed on the first insulating film 11. A connecting hole 22 whose bottom is connected to the first wiring layer 12 is formed in the second insulating film 21. A connecting plug 25 consisting of single crystal of copper is filled in the connecting hole 22 without disposition of other copper crystal therein. A wiring groove 23 whose bottom is connected to the connecting hole 22 is formed on the surface of the second insulating film 21. A second wiring layer 26 is formed from a conductive material disposed in the wiring groove 23. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有由铜构成的通路并具有高SM容限的半导体器件。解决方案：半导体器件包括形成在半导体衬底1上并具有形成在半导体衬底1的表面上的连接区域3的有源元件结构2.第一绝缘膜11设置在半导体衬底1的上方在第一绝缘膜11的表面上设置由铜构成的第一布线层12，在第一绝缘膜11上配置有第二绝缘膜21.底部与第一布线层12连接的连接孔22是形成在第二绝缘膜21中。由铜的单晶组成的连接插头25填充在连接孔22中，而不在其中设置其它铜晶体。在第二绝缘膜21的表面上形成有底部连接到连接孔22的布线槽23.第二布线层26由设置在布线槽23中的导电材料形成。版权所有（C））2005年，日本特许厅和NCIPI

9. 发明专利

JP2013171869A Semiconductor chip and semiconductor wafer 审中-公开
标题翻译：半导体芯片和半导体晶片
公开(公告)号：JP2013171869A
公开(公告)日：2013-09-02
申请号：JP2012033097
申请日：2012-02-17
申请人： Toshiba Corp , 株式会社東芝
发明人： TSUMURA KAZUMICHI , AZUMA KAZUYUKI
IPC分类号： H01L25/065 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L25/07 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip that has a structure capable of optically measuring a misalignment amount between chips.SOLUTION: A semiconductor chip includes: a semiconductor substrate 101 having a first primary surface S1, a second primary surface S2 located opposite to the first primary surface, and a side surface S3 in which at least one groove 111 is formed; and at least one layer 102 formed on the first primary surface of the semiconductor substrate. The chip further includes a first electrode 103 formed so as to penetrate through the semiconductor substrate, and a second electrode 104 formed so as to penetrate through the at least one layer and so as to be in contact with the first electrode. The groove extends from the second primary surface to the first primary surface and terminates at the interface between the semiconductor substrate and the layer or in the layer.
摘要翻译：要解决的问题：提供具有能够光学地测量芯片之间的未对准量的结构的半导体芯片。解决方案：半导体芯片包括：具有第一主表面S1的半导体衬底101，与第一主表面S2相对的第二主表面S2 第一主表面和形成至少一个凹槽111的侧表面S3; 以及形成在半导体衬底的第一主表面上的至少一个层102。芯片还包括形成为穿透半导体衬底的第一电极103和形成为穿透至少一个层并且与第一电极接触的第二电极104。凹槽从第二主表面延伸到第一主表面并且终止于半导体衬底与层之间或层中的界面处。

10. 发明专利

JP2013004863A Semiconductor chip, semiconductor chip manufacturing method and semiconductor device 有权
标题翻译：半导体芯片，半导体芯片制造方法和半导体器件
公开(公告)号：JP2013004863A
公开(公告)日：2013-01-07
申请号：JP2011136449
申请日：2011-06-20
申请人： Toshiba Corp , 株式会社東芝
发明人： TSUMURA KAZUMICHI , AZUMA KAZUYUKI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/562 , H01L21/76802 , H01L21/76898 , H01L23/481 , H01L23/585 , H01L24/16 , H01L25/0657 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/12042 , H01L2924/00 , H01L2224/0401
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip excellent in characteristics and highly reliable, and provide a manufacturing method of the semiconductor chip and a semiconductor device.SOLUTION: A semiconductor chip of a present embodiment comprises: a semiconductor substrate having a first principal surface and a second principal surface, on which a circuit part with an element and wiring being arranged and a guard ring mechanism part surrounding the circuit part are provided on the first principal surface side; a via provided in a via hole opening from the first principal surface side to the second principal surface side; and an insulation layer provided in a first trench leading from the first principal surface side to the second principal surface side. The via hole is arranged in a circuit region, in which the circuit part is provided, when viewed from a direction perpendicular to the first principal surface. The first trench is arranged in an outer peripheral region surrounding the circuit part, in which the guard ring mechanism part is provided. A width of the first trench in a direction parallel with the first principal surface is narrower than a width of the via hole in the direction parallel with the first principal surface.
摘要翻译：解决的问题：提供优异的特性和高可靠性的半导体芯片，并提供半导体芯片和半导体器件的制造方法。解决方案：本实施例的半导体芯片包括：具有第一主表面和第二主表面的半导体衬底，其上布置有元件和布线的电路部分和围绕电路部分的保护环机构部分设置在第一主表面侧; 通孔，设置在从所述第一主表面侧向所述第二主面侧开口的通路孔中; 以及设置在从第一主表面侧到第二主表面侧的第一沟槽中的绝缘层。当从垂直于第一主表面的方向观察时，通孔设置在其中设置有电路部分的电路区域中。第一沟槽布置在围绕电路部分的外周区域中，其中设置有保护环机构部分。在与第一主表面平行的方向上的第一沟槽的宽度比通孔在与第一主表面平行的方向上的宽度窄。版权所有（C）2013，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式