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1. 发明专利

JP2014090202A Trench gate type semiconductor device, and method for manufacturing the same 有权
标题翻译： TRENCH门式半导体器件及其制造方法
公开(公告)号：JP2014090202A
公开(公告)日：2014-05-15
申请号：JP2014000346
申请日：2014-01-06
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： NAKAMURA SHUNICHI , KAWADA YASUYUKI
IPC分类号： H01L29/78 , H01L21/336 , H01L27/04 , H01L29/12 , H01L29/47 , H01L29/739 , H01L29/872
CPC分类号： H01L29/66666 , H01L21/02378 , H01L21/0337 , H01L21/265 , H01L21/28008 , H01L21/308 , H01L29/0623 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/47 , H01L29/66068 , H01L29/66522 , H01L29/66848 , H01L29/7806 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide a trench gate type semiconductor device in which a cell pitch can be reduced by using a wide band gap semiconductor as a main semiconductor substrate, good ohmic contact can be obtained, and an excessive electric field is not applied to an insulating film in a bottom of a trench.SOLUTION: In a method for manufacturing a trench gate type MOSFET, as a method for forming an intersection trench 10p, a gate trench 10b is formed as a double trench structure. Then the gate trench 10b is backfilled with mask material, and the mask material is then patterned, and the patterned mask material is used as a mask for forming the intersection trench. The intersection trench 10p intersecting the gate trench is provided so as to be deeper than the gate trench 10b. A Schottky electrode 24 is provided in a bottom of the intersection trench 10p.
摘要翻译：要解决的问题：为了提供可以通过使用宽带隙半导体作为主要半导体衬底来减小电池间距的沟槽栅型半导体器件，可以获得良好的欧姆接触，并且不会施加过大的电场在沟槽底部的绝缘膜。解决方案：在用于制造沟槽栅型MOSFET的方法中，作为形成交叉沟槽10p的方法，形成栅沟槽10b作为双沟槽结构。然后用掩模材料回填栅极沟槽10b，然后对掩模材料进行图案化，并且将图案化掩模材料用作形成交叉沟槽的掩模。设置与栅极沟槽相交的交叉沟槽10p，以比栅极沟槽10b更深。肖特基电极24设置在交叉沟槽10p的底部。

2. 发明专利

JP2014123768A Silicon carbide semiconductor element manufacturing method and silicon carbide semiconductor element 有权
标题翻译：硅碳化硅半导体元件制造方法和碳化硅半导体元件
公开(公告)号：JP2014123768A
公开(公告)日：2014-07-03
申请号：JP2014040546
申请日：2014-03-03
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： KAWADA YASUYUKI , TAWARA TAKESHI
IPC分类号： H01L29/78 , H01L21/3065 , H01L21/336 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor element manufacturing method and a silicon carbide semiconductor element, which can reduce element defect.SOLUTION: A silicon carbide semiconductor element 100 comprises a trench 1 in which a trench connection part 5 is connected to a trench linear part 2. The trench linear part 2 includes a first line constitution part 2a and a second line constitution part 2b which are arranged in parallel with each other. The trench connection part 5 includes a first connection constitution part 3 perpendicular to the trench linear part 2, a second connection constitution part 4a for connecting the first line constitution part 2a and the first connection constitution part 3, and a third connection constitution part 4b for connecting the second line constitution part 2b and an extension of the first connection constitution part 3. An angle between the second connection constitution part 4a and the first line constitution part 2a is 30 degrees. An angle between the third connection constitution part 4b and an extension of the second line constitution part 2b is 30 degrees.
摘要翻译：要解决的问题：提供可以减少元件缺陷的碳化硅半导体元件制造方法和碳化硅半导体元件。解决方案：碳化硅半导体元件100包括沟槽1，其中沟槽连接部分5连接到沟槽直线部分2包括彼此平行布置的第一线构成部分2a和第二线构成部分2b。沟槽连接部分5包括垂直于沟槽线性部分2的第一连接构造部分3，用于连接第一线路构成部分2a和第一连接构造部分3的第二连接构造部分4a和用于连接第二线路构成部分2b和第一连接构造部分3的延伸部分。第二连接构造部分4a和第一线路结构部分2a之间的角度为30度。第三连接构造部4b与第二线构成部2b的延伸之间的角度为30度。

3. 发明专利

JP2015015486A トレンチゲート型半導体装置の製造方法有权
标题翻译：制造闸门型半导体器件的方法
公开(公告)号：JP2015015486A
公开(公告)日：2015-01-22
申请号：JP2014172750
申请日：2014-08-27
申请人：富士電機株式会社 , Fuji Electric Co Ltd
发明人： NAKAMURA SHUNICHI , KAWADA YASUYUKI
IPC分类号： H01L29/12 , H01L27/04 , H01L29/47 , H01L29/739 , H01L29/78 , H01L29/872
CPC分类号： H01L29/66666 , H01L21/02378 , H01L21/0337 , H01L21/265 , H01L21/28008 , H01L21/308 , H01L29/0623 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/47 , H01L29/66068 , H01L29/66522 , H01L29/66848 , H01L29/7806 , H01L29/7813
摘要：【課題】ワイドバンドギャップ半導体を主たる半導体基板として用い、セルピッチを縮小することができ、良好なオーミック接触が得られ、トレンチ底の絶縁膜に過大な電界が印加されないトレンチゲート型半導体装置を提供すること。【解決手段】交差トレンチ10pの形成方法として、二重トレンチ構造としたゲートトレンチ10bを形成した後に、当該ゲートトレンチ10bをマスク材料で埋め戻し、その後、当該マスク材料をパターニングして、交差トレンチを形成するためのマスクとして用い、ゲートトレンチに交差する交差トレンチ10pをゲートトレンチ10bよりも深く設け、交差トレンチ10p底部にショットキー電極24を設けるトレンチゲート型MOSFETの製造方法とする。【選択図】図50
摘要翻译：要解决的问题：为了提供使用宽带隙半导体作为主半导体衬底的沟槽栅型半导体器件，可以减小电池间距，可以获得优异的欧姆接触，并且不施加过大的电场涉及沟槽底部的绝缘膜。解决方案：在用于制造沟槽栅型MOSFET的方法中，作为形成交叉沟槽10p的方法，形成栅沟槽10b作为双沟槽结构。然后，用掩模材料回填栅极沟槽10b，然后对掩模材料进行图案化，并且将图案化掩模材料用作形成交叉沟槽的掩模。设置与栅极沟槽相交的交叉沟槽10p，以比栅极沟槽10b更深。肖特基电极24设置在交叉沟槽10p的底部。

4. 发明专利

JP2014099483A Silicon carbide semiconductor device manufacturing method 有权
标题翻译：硅碳化硅半导体器件制造方法
公开(公告)号：JP2014099483A
公开(公告)日：2014-05-29
申请号：JP2012249763
申请日：2012-11-13
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： KAWADA YASUYUKI , YONEZAWA YOSHIYUKI
IPC分类号： H01L21/205 , C23C16/42 , C30B25/20 , C30B29/36 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L21/02529 , C30B25/10 , C30B25/16 , C30B25/20 , C30B29/36 , H01L21/02378 , H01L21/0262 , H01L21/0445 , H01L29/045 , H01L29/1608 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a silicon carbide semiconductor device having a long carrier lifetime without performing an additional process after manufacturing an SiC single crystal substrate by a chemical vapor deposition method.SOLUTION: A silicon carbide semiconductor device manufacturing method comprises: adjusting a temperature inside a reaction furnace to 1700°C (step S5); subsequently, introducing a material gas, an added gas, a doping gas and a carrier gas into the reaction furnace (step S6); subsequently, growing an SiC epitaxial film on a surface of a 4H-SiC substrate by a CVD method (step S7); subsequently, cooling the 4H-SiC substrate on which the SiC epitaxial film is stacked in an atmosphere of a hydrogen gas diluted methyl methane gas until the temperature inside the reaction furnace decreases from 1700°C to 1300°C (step S8); and subsequently, cooling the 4H-SiC substrate on which the SiC epitaxial film is stacked in a hydrogen gas atmosphere until the temperature inside the reaction furnace decreases to a temperature lower than 1300°C (step S9).
摘要翻译：要解决的问题：提供一种具有长载流子寿命的碳化硅半导体器件的制造方法，而不需要通过化学气相沉积方法在制造SiC单晶衬底之后执行附加工艺。解决方案：一种碳化硅半导体器件制造方法包括：将反应炉内的温度调节至1700℃（步骤S5）; 随后将材料气体，添加的气体，掺杂气体和载气引入反应炉中（步骤S6）; 随后，通过CVD法在4H-SiC衬底的表面上生长SiC外延膜（步骤S7）; 随后，在氢气稀释的甲基甲烷气体的气氛中冷却其上层叠有SiC外延膜的4H-SiC衬底，直到反应炉内的温度从1700℃降低到1300℃（步骤S8）; 然后在氢气气氛中冷却SiC外延膜层叠的4H-SiC基板，直到反应炉内的温度降低到低于1300℃的温度（步骤S9）。

5. 发明专利

JP2014053511A Silicon carbide semiconductor device manufacturing method 有权
标题翻译：硅碳化硅半导体器件制造方法
公开(公告)号：JP2014053511A
公开(公告)日：2014-03-20
申请号：JP2012197948
申请日：2012-09-07
申请人： Fuji Electric Co Ltd , 富士電機株式会社 , Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KAWADA YASUYUKI , TOMITA NOBUYUKI
IPC分类号： H01L21/205 , C23C16/42
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device manufacturing method which can grow a silicon carbide semiconductor film having high crystal quality at high speed.SOLUTION: A silicon carbide semiconductor device manufacturing method comprises: introducing a material gas, an added gas, a doping gas and a carrier gas into a reacting furnace (step S5); and subsequently growing an SiC epitaxial film on a surface of a 4H-SiC substrate in a CVD method by using the material gas, the added gas, the doping gas and the carrier gas to manufacture an SiC single crystal substrate (step S6). As the material gas, an Si-containing gas and a C-containing gas are used. As the added ga, a Cl-containing gas and a F-containing gas are used. As a carrier gas, an Hgas is used. The gas which contains Cl within a range where a ratio of the number of Cl atoms to the number of Si atoms in the Si-containing gas is 2.0 or more and 5.0 or less is added. The gas which contains F within a range where a ratio of the number of F atoms to the number of H atoms in the carrier gas is 0.1 or more and 0.2 or less is added.
摘要翻译：要解决的问题：提供一种可以高速生长具有高晶体质量的碳化硅半导体膜的碳化硅半导体器件制造方法。解决方案：一种碳化硅半导体器件的制造方法，包括：引入原料气体，添加的气体，掺杂气体和载气进入反应炉（步骤S5）; 然后通过使用原料气体，添加的气体，掺杂气体和载气在CVD法中在4H-SiC衬底的表面上生长SiC外延膜，制造SiC单晶衬底（步骤S6）。作为原料气体，使用含Si气体和含C气体。作为添加的ga，使用含Cl的气体和含F的气体。作为载气，使用H气。在含有气体中的Cl原子数与Si原子数的比例为2.0以上且5.0以下的范围内含有Cl的气体。在载体气体中F原子数与H原子数的比例为0.1以上且0.2以下的范围内含有F的气体。

6. 发明专利

JP2015019092A トレンチゲート型半導体装置有权
标题翻译： TRENCH-GATE半导体器件
公开(公告)号：JP2015019092A
公开(公告)日：2015-01-29
申请号：JP2014172749
申请日：2014-08-27
申请人：富士電機株式会社 , Fuji Electric Co Ltd
发明人： NAKAMURA SHUNICHI , KAWADA YASUYUKI
IPC分类号： H01L29/12 , H01L27/04 , H01L29/739 , H01L29/78 , H01L29/872
CPC分类号： H01L29/66666 , H01L21/02378 , H01L21/0337 , H01L21/265 , H01L21/28008 , H01L21/308 , H01L29/0623 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/47 , H01L29/66068 , H01L29/66522 , H01L29/66848 , H01L29/7806 , H01L29/7813
摘要：【課題】ワイドバンドギャップ半導体を主たる半導体基板として用い、セルピッチを縮小することができ、良好なオーミック接触が得られ、トレンチ底の絶縁膜に過大な電界が印加されないトレンチゲート型半導体装置MOSFETを提供する。【解決手段】交差トレンチ10pの形成方法として、二重トレンチ構造としたゲートトレンチ10bを形成した後に、ゲートトレンチ10bをマスク材料で埋め戻し、その後、当該マスク材料をパターニングして、交差トレンチを形成するためのマスクとして用い、ゲートトレンチに交差する交差トレンチ10pをゲートトレンチ10bよりも深く設け、交差トレンチ10p底部にショットキー電極24を設ける。【選択図】図50
摘要翻译：要解决的问题：提供主要使用宽带隙半导体作为半导体衬底的沟槽栅半导体器件MOSFET; 这可以减少电池间距并获得良好的欧姆接触; 并且其中不对沟槽底部的绝缘膜施加过大的电场。解决方案：在交叉沟槽10p的形成方法中，形成具有双沟槽结构的栅极沟槽10b，随后形成栅极沟槽10b 再次用掩模材料填充掩模材料，然后对掩模材料进行构图并用作形成交叉沟槽的掩模，以形成在深度比栅极沟槽10b的深度更深的深度与栅极沟槽交叉的交叉沟槽10p，并且在交叉沟槽10p的底部上形成肖特基电极24。

7. 发明专利

JP2014047090A Method for producing silicon carbide semiconductor device 有权
标题翻译：生产碳化硅半导体器件的方法
公开(公告)号：JP2014047090A
公开(公告)日：2014-03-17
申请号：JP2012190096
申请日：2012-08-30
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： KAWADA YASUYUKI , YONEZAWA YOSHIYUKI
IPC分类号： C30B29/36 , C30B25/16 , H01L21/205
CPC分类号： H01L21/02529 , C30B25/02 , C30B29/36 , H01L21/02378 , H01L21/0262
摘要： PROBLEM TO BE SOLVED: To provide a method for producing a silicon carbide semiconductor device that enables rapid growth of a silicon carbide semiconductor film.SOLUTION: A method for producing a silicon carbide semiconductor device comprises: S5 of introducing gas containing Si, gas containing C and gas containing Cl in a reaction furnace; S6 (a first step) of growing an SiC epitaxial film on a 4H-SiC substrate by a CVD process in a gas atmosphere consisting of the raw material gas introduced in the step S5, added gas, doping gas and carrier gas; and a second step of gradually reducing the introduction amount ratio of the gas containing Cl to the gas containing Si in the gas atmosphere. At the beginning of the first step, the number of Cl atoms in the gas containing Cl in the gas atmosphere is 3 times of the number of Si atoms in the gas containing Si. In the second step, the number of Cl atoms in the gas containing Cl in the gas atmosphere to the number of Si atoms in the gas containing Si is reduced at the rate of 0.5% per minute to 1.0% per minute.
摘要翻译：要解决的问题：提供一种能够快速生长碳化硅半导体膜的碳化硅半导体器件的制造方法。解决方案：一种制造碳化硅半导体器件的方法，包括：引入含有Si的气体的S5，含有C 和在反应炉中含有Cl的气体; S6（第一步骤）在由在步骤S5中导入的原料气体，添加气体，掺杂气体和载气组成的气体气氛中通过CVD工艺在4H-SiC衬底上生长SiC外延膜; 以及在气体气氛中逐渐降低含有Cl的气体与含有Si的气体的引入量比的第二步骤。在第一步开始时，气体气氛中含有Cl的气体中的Cl原子数是含有Si的气体中的Si原子数的3倍。在第二步骤中，含有气体气氛中的Cl的气体中的Cl原子数与含有Si的气体中的Si原子数目以每分钟0.5％的速率降低至1.0％/分钟。

8. 发明专利

JP2013051435A Method of manufacturing silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：JP2013051435A
公开(公告)日：2013-03-14
申请号：JP2012243974
申请日：2012-11-05
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： KAWADA YASUYUKI , TAWARA TAKESHI , NAKAMURA SHUNICHI , GOTO MASAHIDE
IPC分类号： H01L21/28 , H01L21/336 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicon carbide semiconductor device that is low in contact resistance between an electrode film and a wiring conductor element piece, and in which the wiring conductor element piece is hardly peeled off from the electrode film.SOLUTION: On a surface of an n-type silicon carbide substrate or an n-type silicon carbide region 1, a nickel film 2 and a nickel oxide film 3 are laminated in this order and then heat-treated in a state of not being subjected to oxidation. By performing such heat treatment, a part of the nickel film 2 becomes a nickel silicide film 4. After that, the nickel oxide film 3 is removed with a hydrochloric acid solution, and on a surface of the nickel silicide film 4, a nickel aluminum film 5 and an aluminum film 6 are laminated in this order.
摘要翻译：要解决的问题：提供一种制造电极膜和布线导体元件之间的接触电阻低的碳化硅半导体器件的方法，并且其中布线导体元件片几乎不从电极膜。解决方案：在n型碳化硅衬底或n型碳化硅区域1的表面上，依次层压镍膜2和氧化镍膜3，然后以不被氧化。通过进行这样的热处理，镍膜2的一部分成为硅化镍膜4.之后，用盐酸溶液除去氧化镍膜3，在硅化镍膜4的表面上形成镍铝膜5和铝膜6依次层叠。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JPH09145656A CONTACT BURNING TYPE GAS SENSOR 失效
公开(公告)号：JPH09145656A
公开(公告)日：1997-06-06
申请号：JP30552695
申请日：1995-11-24
申请人： FUJI ELECTRIC CO LTD
发明人： KAWADA YASUYUKI , TSUDA KOICHI
IPC分类号： G01N25/22 , G01N27/16
摘要： PROBLEM TO BE SOLVED: To provide the contact burning type gas sensor having higher selectivity than hydrogen gas with respect to carbon monoxide gas. SOLUTION: This gas sensor comprises a gas detecting element 3, which is formed by attaching a carrier 2 of a metal-oxide sintered body supporting catalyst to a temperature measuring resistor 1, and a compensating element, which is formed by attaching the carrier of the same metal-oxide sintered body that does not support the catalyst to the same temperature measuring resistor. At this time, the oxidizing property of the above described catalyst for the carbon dioxide gas is made to be higher than the oxidizing property for the hydrogen gas. The carrier 2 is formed of γ alumina, and the above described catalyst is formed of the ruthenium or the mixture of ruthenium and rhodium.

10. 发明专利

JPH0875692A CONTACT-BURNING TYPE GAS SENSOR 失效
公开(公告)号：JPH0875692A
公开(公告)日：1996-03-22
申请号：JP28624894
申请日：1994-11-21
申请人： FUJI ELECTRIC CO LTD
发明人： ICHIMURA TAKESHIGE , KAWADA YASUYUKI , TSUDA KOICHI , NUMATA JUNKO
IPC分类号： G01N27/16
摘要： PURPOSE: To provide a contact-burning type gas sensor for carbon monoxide gas, which has high sensitivity, excellent selectivity and excellent reliability. CONSTITUTION: A gas detecting part and a temperature compensating part are assembled in the branch side of a Wheatstone bridge circuit. The gas detecting part comprises a metal wire 1, which is wound around a supporter 2 that is the poor conductor of heat and an oxidized burning layer 3 coating the metal wire 1. The oxidized burning layer 3 is constituted of ferric oxide carrier supporting gold. The temperature compensating part is constituted of a metal wire, which is wound around the supporter that is the poor conductor of heat.

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