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1. 发明专利

JP4648940B2 The manufacturing method for a variable resistive element 有权
公开(公告)号：JP4648940B2
公开(公告)日：2011-03-09
申请号：JP2007282261
申请日：2007-10-30
申请人：シャープ株式会社
发明人：貴司中野 , 雄史井上 , 哲也大西 , 信夫山崎 , 隆広渋谷 , 数也石原 , 康成細井
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00

2. 发明专利

JP5161946B2 Non-volatile semiconductor memory device 有权
公开(公告)号：JP5161946B2
公开(公告)日：2013-03-13
申请号：JP2010221877
申请日：2010-09-30
申请人：シャープ株式会社
发明人：優川端 , 信夫山崎 , 数也石原 , 潤哉大西 , 信義粟屋 , 幸夫玉井
IPC分类号： G11C13/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C2013/0071 , G11C2013/0073 , G11C2013/0083 , G11C2213/79
摘要： A nonvolatile semiconductor memory device includes a memory cell array for storing user data provided by arranging memory cells each having a variable resistive element having a first electrode, a second electrode, and a variable resistor made of a metal oxide sandwiched between the first and second electrodes. The first and second electrodes are formed of a conductive material forming ohmic junction with the variable resistor and a conductive material forming non-ohmic junction with the variable resistor, respectively. The variable resistor changes between two or more different resistance states by applying a voltage between the electrodes. The resistance state after being changed is maintained in a nonvolatile manner. The variable resistive elements of all memory cells in the memory cell array are set to the highest of the two or more different resistance states in an unused state before the memory cell array is used to store the user data.

3. 发明专利

JP4088324B1 Non-volatile semiconductor memory device 有权
公开(公告)号：JP4088324B1
公开(公告)日：2008-05-21
申请号：JP2006331689
申请日：2006-12-08
申请人：シャープ株式会社
发明人：信夫山崎 , 研一田中 , 信義粟屋 , 康成細井 , 眞一里
IPC分类号： H01L27/10 , G11C13/00 , H01L45/00 , H01L49/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/003 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , G11C2213/76 , G11C2213/77 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.

4. 发明专利

JP5156060B2 Non-volatile semiconductor memory device 有权
公开(公告)号：JP5156060B2
公开(公告)日：2013-03-06
申请号：JP2010171079
申请日：2010-07-29
申请人：シャープ株式会社
发明人：潤哉大西 , 信夫山崎 , 数也石原 , 雄史井上 , 幸夫玉井 , 信義粟屋
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146

5. 发明专利

JP5091999B2 Semiconductor memory device 有权
公开(公告)号：JP5091999B2
公开(公告)日：2012-12-05
申请号：JP2010214009
申请日：2010-09-24
申请人：シャープ株式会社
发明人：満名倉 , 数也石原 , 信夫山崎 , 優川端
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0028 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C13/0097

6. 发明专利

JP4880894B2 Structure and method of manufacturing the semiconductor memory device 有权
公开(公告)号：JP4880894B2
公开(公告)日：2012-02-22
申请号：JP2004333130
申请日：2004-11-17
申请人：シャープ株式会社
发明人：貴司中野 , 哲也大西 , 茂夫大西 , 信夫山崎 , 尚之新村 , 隆広渋谷 , 雅之田尻
IPC分类号： H01L27/105 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes (2) arranged to extend in one direction, and a plurality of lower electrodes (1) arranged to extend in another direction at a right angle to the one direction of the upper electrodes (2). Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

7. 发明专利

JP4829502B2 A method of manufacturing a semiconductor memory device 有权
公开(公告)号：JP4829502B2
公开(公告)日：2011-12-07
申请号：JP2005003799
申请日：2005-01-11
申请人：シャープ株式会社
发明人：貴司中野 , 哲也大西 , 茂夫大西 , 信夫山崎 , 尚之新村 , 隆広渋谷 , 雅之田尻
IPC分类号： H01L27/105 , H01L45/00
CPC分类号： H01L45/1675 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641
摘要： The present invention is directed towards a method of manufacturing a semiconductor memory device arranged of a cross point memory array having memory elements provided between upper and lower electrodes for storage of data. The present invention comprises a lower electrode lines forming step of planarizing each of the lower electrode lines and insulating layers provided on both sides of the lower electrode line so as to be substantially uniform in the height thus for patterning the lower electrode lines, a memory element layer depositing step of depositing on the lower electrode lines a memory element layer for the memory elements, and an annealing step of annealing with heat treatment either between the lower electrode lines forming step and the memory element layer depositing step or after the memory element layer depositing step so that any damages caused by the polishing of the surface of the lower electrode lines can be eliminated.

8. 发明专利

JP5351863B2 Control method for a nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device 有权
公开(公告)号：JP5351863B2
公开(公告)日：2013-11-27
申请号：JP2010209650
申请日：2010-09-17
申请人：シャープ株式会社
发明人：優川端 , 信夫山崎
IPC分类号： G11C13/00
摘要： PROBLEM TO BE SOLVED: To effectively prevent a deterioration in a variable resistive element of an RRAM by suppressing variations of resistive states. SOLUTION: A memory cell array 10 provided with a plurality of memory cells M provided with a variable resistive element R whose electric resistance changes to two or more different resistive states, a determination circuit for partitioning the range of resistance values, which the variable resistive element R can take, into a plurality of target ranges and a plurality of middle ranges and determining whether the resistance value of the memory cell M is within any range among the plurality of target ranges and the plurality of middle ranges, and a write circuit 13 for applying a voltage pulse to the variable resistive element R so as to make a resistance value be within one range among the target ranges and writing information in the memory cells M are provided. Two or more middle ranges exist between two adjacent target ranges. In the determination circuit, a voltage pulse is applied to a memory cell M in which the resistance value of the memory cell M is not determined to be within a predetermined target range on a first application condition set differently at least in each middle range. COPYRIGHT: (C)2012,JPO&INPIT

9. 发明专利

JP4238248B2 Method of manufacturing a nonvolatile semiconductor memory device including a variable resistance element 有权
公开(公告)号：JP4238248B2
公开(公告)日：2009-03-18
申请号：JP2005327982
申请日：2005-11-11
申请人：シャープ株式会社
发明人：信夫山崎
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： H01L27/101 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： This invention provides a process for producing a nonvolatile semiconductor memory device that can suppress a variation in resistance value derived from the difference in degree of crystallization of PCMO in variable resistors and can satisfactorily ensure a circuit operation margin. The production process is a process for producing a semiconductor memory device comprising a variable resistor for storing data between upper and lower electrodes and comprises a variable resistor formation step of sputtering an electrically conductive metal oxide in an oxygen-free atmosphere to form the variable resistor.

10. 发明专利

JP5222380B2 Forming processing method and a nonvolatile semiconductor memory device of the variable resistance element 有权
公开(公告)号：JP5222380B2
公开(公告)日：2013-06-26
申请号：JP2011115559
申请日：2011-05-24
申请人：シャープ株式会社
发明人：信夫山崎 , 数也石原 , 優川端
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C13/0007 , G11C2013/0083 , G11C2013/009 , G11C2013/0092 , G11C2213/32 , H01L27/2436 , H01L45/08 , H01L45/1226 , H01L45/1266 , H01L45/146
摘要： A method of a forming process for a variable resistive element, which is performed in short time comparable to the pulse forming and a writing current in a switching action is the same level as that of the DC forming, is provided. In the forming process, a variable resistive element is changed by voltage pulse application from an initial high resistance state just after produced to a variable resistance state where the switching action is performed. The forming process includes a first step of applying a first pulse having a voltage amplitude lower than a threshold voltage at which the resistance of the variable resistive element is lowered, to between both electrodes of the variable resistive element, and a second step of applying a second pulse having a voltage amplitude having the same polarity as the first pulse and not lower than the threshold voltage, thereto after the first step.

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