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1. 发明专利

JP5328594B2 Spread structure 有权
公开(公告)号：JP5328594B2
公开(公告)日：2013-10-30
申请号：JP2009231067
申请日：2009-10-04
申请人：内田紙工業株式会社 , アイ・デザイン株式会社
发明人：和行内田
IPC分类号： B42D15/04 , B42D15/02 , G09F1/08
摘要： PROBLEM TO BE SOLVED: To provide a double-spread structure which has good appearance, is easy to manufacture, and allows to surely raise a stand-up area. SOLUTION: An inner sheet 20 is stuck, across a fold 14, to the inside of a board 12 having continuously connected sheets 16 and 18 foldable along the fold 14. The inner sheet 20 is provided with a stand-up area 24 rising during opening/closing of the board 12, a cut line 26 and stand-up guide lines 22, 28, 30 for forming the stand-up area 24, and a support area 32. By perforating the stand-up guide lines 22, 28, 30, the stand-up area 24 is surely raised, and manufacturing is facilitated. Because of no fold in the stand-up area 24, good appearance is not impaired. The stand-up guide lines 22, 28, 30 are formed in a direction roughly orthogonal to the paper grain of the inner sheet 20, thus the stand-up area 24 is more surely raised. COPYRIGHT: (C)2011,JPO&INPIT

2. 发明专利

JP2011079150A Double spread structure 有权
标题翻译：双重传播结构
公开(公告)号：JP2011079150A
公开(公告)日：2011-04-21
申请号：JP2009231067
申请日：2009-10-04
申请人： I-Design Corp , Uchida Shikogyo Kk , アイ・デザイン株式会社 , 内田紙工業株式会社
发明人： UCHIDA KAZUYUKI
IPC分类号： B42D15/04
摘要： PROBLEM TO BE SOLVED: To provide a double-spread structure which has good appearance, is easy to manufacture, and allows to surely raise a stand-up area. SOLUTION: An inner sheet 20 is stuck, across a fold 14, to the inside of a board 12 having continuously connected sheets 16 and 18 foldable along the fold 14. The inner sheet 20 is provided with a stand-up area 24 rising during opening/closing of the board 12, a cut line 26 and stand-up guide lines 22, 28, 30 for forming the stand-up area 24, and a support area 32. By perforating the stand-up guide lines 22, 28, 30, the stand-up area 24 is surely raised, and manufacturing is facilitated. Because of no fold in the stand-up area 24, good appearance is not impaired. The stand-up guide lines 22, 28, 30 are formed in a direction roughly orthogonal to the paper grain of the inner sheet 20, thus the stand-up area 24 is more surely raised. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供外观美观，易于制造的双扩展结构，并且可以确保提高起始区域。解决方案：内部片材20穿过折叠部分14被粘贴到具有连续连接的片材16和18的板12的内侧，折叠部分14和18可沿着折叠部分14折叠。内部片材20设置有支撑区域24 在板12的打开/关闭期间上升，切割线26和用于形成支撑区域24的竖立引导线22,28,30以及支撑区域32.通过对直立引导线22进行穿孔，如图28,30所示，立起区域24可靠地提高，制造便利。由于在直立区域24中没有褶皱，良好的外观不会受损。立式引导线22,28,30形成在与内片20的纸粒大致正交的方向上，从而可靠地提高立起部24。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2007069346A Printed matter for publicity/advertizement 有权
标题翻译：公开/广告印刷事宜
公开(公告)号：JP2007069346A
公开(公告)日：2007-03-22
申请号：JP2004066621
申请日：2004-03-10
申请人： I-Design Corp , Uchida Shikogyo Kk , アイ・デザイン株式会社 , 内田紙工業株式会社
发明人： UCHIDA KAZUYUKI
IPC分类号： B42D11/00 , B42D15/10 , G09F5/04
CPC分类号： A45D40/0087 , B42D15/025 , B42D15/027 , G09F5/04 , G09F23/10
摘要： PROBLEM TO BE SOLVED: To provide a printed matter for publicity/advertizement, which is so devised as to let a consumer have more interest in addition to the addition of a sales promotion medium (a giveaway). SOLUTION: The printed matter 1 for publicity/advertizement is equipped with a base 3, a printing layer 20 printed on the base 3, a sales promotion medium 40 consisting of goods and service placed on the printing layer and a scrapable bonding layer 30, which is formed on the printing layer and used for bonding the sales promotion medium 40. The printing layer 20, which emerges by scraping away the bonding layer 30, and the bonding layer 30 relate with the actions and effects of the goods or service intending for publicity/advertizement. By providing the scrapable bonding layer 30, after the removal of the sales promotion medium (the giveaway), the scraping-away conduct of the bonding layer is caused. Through the conduct, a consumer discovers something and comes to have interest and curiosity. The interest and curiosity relate with the elevation of the directivity towards the target goods and service, resulting in heightening a publicity/advertizement effect. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供用于宣传/广告的印刷品，其设计为让消费者除了添加促销媒体（赠品）之外，还有更多的兴趣。
解决方案：用于宣传/广告的印刷品1配备有基座3，印刷在基座3上的印刷层20，由放置在印刷层上的商品和服务组成的促销介质40和可剥离的粘结层 30，其形成在印刷层上并用于粘合销售促进介质40.通过刮去粘合层30而出现的印刷层20和粘结层30与商品或服务的作用和效果有关打算宣传/广告。通过设置可剥离接合层30，在去除促销介质（赠品）之后，引起接合层的剥离导电。通过这种行为，消费者发现了一些东西，并有兴趣和好奇心。兴趣和好奇心与目标商品和服务的方向性提高有关，导致宣传/广告效应的提高。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2003076739A Apparatus, method and program for logical verification 审中-公开
标题翻译：用于逻辑验证的装置，方法和程序
公开(公告)号：JP2003076739A
公开(公告)日：2003-03-14
申请号：JP2001267584
申请日：2001-09-04
申请人： Mitsubishi Electric Corp , Mitsubishi Electric System Lsi Design Corp , 三菱電機システムエル・エス・アイ・デザイン株式会社 , 三菱電機株式会社
发明人： MIKAWA YUKIHARU , HAMANO HIROYUKI
IPC分类号： G01R31/28 , G06F17/50 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To solve the problem wherein it is impossible to perform a precise logical verification of connecting parts with abnormal voltages in a logical circuit.
SOLUTION: An apparatus for logical verification comprises a logical model simulating logical operations of logical elements composing a logical circuit, a file of voltage value information storing voltage value information defining pressure-resistant characteristics of electric elements composing the logical elements, a processing model, which is installed into the logical model, for voltage value information reading out voltage value information set in itself from the file of the voltage value information to compare with the voltage value information when the voltage value information is input and determining whether it is possible or not for voltage values input from outside to be accepted by the electric elements corresponding to itself based on the result of the comparison and a performing means of logical verification performing the logical verification of the logical circuit using the logical model based on the test pattern and the connecting information of the logical elements described in a net list of the logical circuit and also verifying the connecting parts with abnormal voltages according to a result of determination acquired by transmission of each voltage value information among each processing model.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了解决在逻辑电路中不可能执行具有异常电压的连接部分的精确逻辑验证的问题。解决方案：用于逻辑验证的装置包括模拟构成逻辑电路的逻辑元件的逻辑运算的逻辑模型，存储定义构成逻辑元件的电气元件的耐压特性的电压值信息的电压值信息的文件，处理模型被安装到逻辑模型中，对于电压值信息从电压值信息的文件读出本身设置的电压值信息，以便在输入电压值信息时与电压值信息进行比较，并且确定是否可能根据比较结果，从外部输入的电压值由与其自身对应的电气元件接受，以及执行基于测试图案和连接信息的使用逻辑模型的逻辑电路的逻辑验证的逻辑验证手段的逻辑元素d 在逻辑电路的网络列表中，并根据通过每个处理模型中的每个电压值信息的传输获取的确定结果来验证具有异常电压的连接部分。

5. 发明专利

JP2003037971A Testing circuit and testing method for voltage step-up circuit 审中-公开
标题翻译：电压升压电路的测试电路和测试方法
公开(公告)号：JP2003037971A
公开(公告)日：2003-02-07
申请号：JP2001222094
申请日：2001-07-23
申请人： Mitsubishi Electric Corp , Mitsubishi Electric System Lsi Design Corp , 三菱電機システムエル・エス・アイ・デザイン株式会社 , 三菱電機株式会社
发明人： UEDA HARUNORI , YOSHIOKA SATOHIRO
IPC分类号： G02F1/133 , H02M3/07
摘要： PROBLEM TO BE SOLVED: To easily carry out testing of a voltage step-up circuit.
SOLUTION: When carrying out testing of the step-up circuit 3a that is constituted of a plurality of transistors and raises a reference voltage, a counter section 1 is caused to set an initial value by a reset signal 52, periodically outputting counter values 51 starting from the set initial value, with a timing control section 2 controlling the continuity of a plurality of transistors by the output counter values 51, and the current passing through the step-up circuit 3a, whose state of connection changes by the counter values 51 constituted of a plurality of continuity-controlled transistors, is measured.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：易于进行升压电路的测试。解决方案：当对由多个晶体管构成的升压电路3a进行测试并提高参考电压时，使计数器部分1通过复位信号52设置初始值，周期性地输出计数器值51开始根据设定的初始值，通过输出计数器值51控制多个晶体管的导通性的定时控制部分2和通过构成的计数器值51的连接状态变化的升压电路3a的电流测量多个导通控制晶体管。

6. 发明专利

JP2003030002A Device and method for supporting test 审中-公开
标题翻译：用于支持测试的设备和方法
公开(公告)号：JP2003030002A
公开(公告)日：2003-01-31
申请号：JP2001218542
申请日：2001-07-18
申请人： Mitsubishi Electric Corp , Mitsubishi Electric System Lsi Design Corp , 三菱電機システムエル・エス・アイ・デザイン株式会社 , 三菱電機株式会社
发明人： TANI TAKAHIRO
IPC分类号： G01R31/28 , G01R31/3183 , G06F11/22
摘要： PROBLEM TO BE SOLVED: To solve problems such as a work to specify where in a machine language instruction an abnormal operation is occurred is difficult since a functional test program is written in terms of binary numbers in failure analysis using an LSI tester. SOLUTION: This device for supporting a test is provided with an extracting means 10 of an address of a nonconformity generating place to extract the address of the nonconformity generating place where instruction fetch is generated based on an instruction fetch signal being sampled by the functional test program and an address bus signal, an extracting part 11 of a comparative error place of an output expected value to extract assembly language description having the same load address as the address of the nonconformity generating place from an assembly list file and a display part 12 of a comparative error place of the output expected value to display the assembly language description so as to be easily specified.
摘要翻译：要解决的问题：为了解决诸如在机器语言指令中发生异常操作的工作的问题，由于在使用LSI测试器的故障分析中以二进制数编写功能测试程序是困难的。解决方案：用于支持测试的该装置具有提取装置10，该提取装置10根据由功能测试程序取样的指令获取信号，提取不符合生成位置的地址的提取装置10，以提取生成指令的不合格生成位置的地址和地址总线信号，输出期望值的比较误差位置的提取部分11，从装配列表文件和显示部分12提取具有与不合格生成位置的地址相同的加载地址的汇编语言描述输出期望值的比较误差位置来显示汇编语言描述，以便于指定。

7. 发明专利

JP2003022699A Evaluating method for data holding capability of non- volatile memory, device therefor, and lsi having evaluation function for data holding capability 审中-公开
标题翻译：用于数据保存能力的非易失性存储器的数据保存能力的评估方法及其具有评估功能的LSI
公开(公告)号：JP2003022699A
公开(公告)日：2003-01-24
申请号：JP2001205133
申请日：2001-07-05
申请人： Mitsubishi Electric Corp , Mitsubishi Electric System Lsi Design Corp , 三菱電機システムエル・エス・アイ・デザイン株式会社 , 三菱電機株式会社
发明人： FUKUSHIMA KAZUHIKO
IPC分类号： G11C16/02 , G11C29/00 , G11C29/06 , G11C29/12 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To enable the data holding capability over a long time of a non- volatile memory to be efficiently evaluated in a short time. SOLUTION: After a control section 32 writes data in a memory cell 31 of a non-volatile memory with the rated voltage output of a charge pump circuit 26, the section 32 switches a selector 27, applies the prescribed stress voltage Vcc being lower than the rating voltage to an oxide film O1 between a floating gate FG1 and a drain D1 of the cell and accelerates disappearance of data. The control section 32 discriminates data holding capability by obtaining a holding time of data detected after applying of stress voltage from a detected value of a sense amplifier NTR1 and a timer 33.
摘要翻译：要解决的问题：为了在短时间内有效地评估非易失性存储器的长时间的数据保持能力。解决方案：控制部分32在电荷泵电路26的额定电压输出的非易失性存储器的存储单元31中写入数据之后，切换选择器27，施加规定的应力电压Vcc低于对电池的浮置栅极FG1和漏极D1之间的氧化膜O1施加额定电压，并加速数据的消失。控制部分32通过从读出放大器NTR1和定时器33的检测值获得施加应力电压之后检测到的数据的保持时间来识别数据保持能力。

8. 发明专利

JP2003022144A Microcomputer oscillation switching circuit 有权
标题翻译：微型振荡器振荡电路
公开(公告)号：JP2003022144A
公开(公告)日：2003-01-24
申请号：JP2001208368
申请日：2001-07-09
申请人： Mitsubishi Electric Corp , Mitsubishi Electric System Lsi Design Corp , 三菱電機システムエル・エス・アイ・デザイン株式会社 , 三菱電機株式会社
发明人： TAKEMOTO JUNICHI
IPC分类号： G06F1/24 , G06F1/06 , H03K5/00 , H03K5/19 , H03K17/00
摘要： PROBLEM TO BE SOLVED: To obtain a microcomputer oscillation switching circuit capable of constantly supplying clock signals without causing troubles in a microcomputer.
SOLUTION: The microcomputer oscillation switching circuit is provided with an oscillation stop detecting circuit to be initialized in response only to a one-shot pulse to be generated only in power application, to detect stop of input of an external clock signal and to output a detection signal and a clock switching circuit to switch and control a clock selection circuit so as to select the external clock signal when the detection signal is initialized and to select a self-oscillation clock signal when the stop of the input of the external clock signal is detected.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：获得能够不间断地提供时钟信号而不引起微机故障的微计算机振荡切换电路。解决方案：微机振荡开关电路设有一个振荡停止检测电路，只有在施加电源才产生单触发脉冲才能被初始化，以检测外部时钟信号的输入停止并输出检测信号和时钟切换电路，用于切换和控制时钟选择电路，以便当检测信号被初始化时选择外部时钟信号，并且当检测到外部时钟信号的输入停止时选择自振荡时钟信号。

9. 发明专利

JP2003016136A Method and device for verifying layout pattern 审中-公开
标题翻译：用于验证布局图案的方法和装置
公开(公告)号：JP2003016136A
公开(公告)日：2003-01-17
申请号：JP2001202221
申请日：2001-07-03
申请人： Mitsubishi Electric Corp , Mitsubishi Electric System Lsi Design Corp , 三菱電機システムエル・エス・アイ・デザイン株式会社 , 三菱電機株式会社
发明人： FUJIMOTO YUTAKA
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To solve the problem that leak current, transistor destruction, etc., frequently occur because not only a verification term becomes long but also verification accuracy of visual observation is low in the conventional layout pattern verifying method.
SOLUTION: This layout pattern verifying method has a step for obtaining P channel transistor extraction data in an N well of a high potential, a step for obtaining power supply wiring extraction data of a low potential, and a step for verifying whether or not the gate of a P channel transistor existing in the N well connected to a power supply wiring of a high potential is connected to a power supply wiring of a low potential on the basis of the P channel transistor extraction data in the N well of a high potential and the power supply wiring extraction data of a low potential.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了解决常规布局图案验证方法中不仅验证项目变长，而且视觉观察的验证精度低的问题，频繁发生漏电流，晶体管损坏等。解决方案：该布局模式验证方法具有用于获得高电位的N阱中的P沟道晶体管提取数据的步骤，用于获得低电位的电源布线提取数据的步骤，以及用于验证栅极存在于连接到高电位的电源布线的N阱中的P沟道晶体管的P沟道晶体管基于高电位的N阱中的P沟道晶体管提取数据而连接到低电位的电源布线，并且电源接线提取数据电位低。

10. 发明专利

JP2003015577A Drive circuit for fluorescent display 审中-公开
标题翻译：用于荧光显示的驱动电路
公开(公告)号：JP2003015577A
公开(公告)日：2003-01-17
申请号：JP2001195003
申请日：2001-06-27
申请人： Mitsubishi Electric Corp , Mitsubishi Electric System Lsi Design Corp , 三菱電機システムエル・エス・アイ・デザイン株式会社 , 三菱電機株式会社
发明人： OKUYAMA KAZUYA
IPC分类号： G09G3/12 , G09G3/04
摘要： PROBLEM TO BE SOLVED: To make segment signals from respective microcomputers to be synchronized with a digit signal.
SOLUTION: A microcomputer 1 incorporates a fluorescent display controller 11 supplying a digit signal and a segment signal to a fluorescent display 3, and a microcomputer 2 incorporates a fluorescent display controller 12 supplying a segment signal to the fluorescent display 3. Then, the fluorescent display controller 11 outputs the digit signal and the segment signal, based on the starting signal by starting instructions of the microcomputer 1, and the second fluorescent display controller 12 supplies the segment signal based on the starting signal.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：使来自各个微型计算机的分段信号与数字信号同步。解决方案：微型计算机1包括向荧光显示器3提供数字信号和分段信号的荧光显示控制器11，微型计算机2包括向荧光显示器3提供分段信号的荧光显示控制器12。控制器11通过启动微型计算机1的指令，基于开始信号输出数字信号和分段信号，第二荧光显示控制器12根据起始信号提供分段信号。

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