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81. 发明专利

JPH06163833A BIMOS SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06163833A
公开(公告)日：1994-06-10
申请号：JP4222891
申请日：1991-02-15
申请人： TOSHIBA CORP
发明人： FUSE TSUNEAKI , HAMAZAKI TOSHIHIKO , MATSUZAWA KAZUYA , WATANABE SHIGEYOSHI
IPC分类号： H01L27/06 , H01L21/8249
摘要： PURPOSE:To constitute a high-speed BiMOS circuit in a lower collector concentration and to contrive to improve the breakdown strength of a BiMOS semiconductor device by a method wherein the speed overshoot of carriers due to a miniaturization of the device and a two-dimensional effect are taken in a formula which shows a base extrusion effect. CONSTITUTION:The density of a collector current in a BiMOS circuit exceeds a boundary current density Jo, which is shown by the following descriptive formula Jo=qv[Nc+2epsilonsi(VCB+phibi)/qWc ], due to the speed overshoot of carriers and a collector impurity concentration Nc and a collector width Wc are set so that the responce time of an output terminal is shortest. In the formula, Jo is a boundary current to begin to generate a base extrusion effect, q is unit charge, v is the speed of carriers generating the speed overshoot, Nc is the collector impurity concentration, epsilonsi is the dielectric constant of a silicon film, VCB is the collector-base voltage, phibi is the built-in voltage of a collector junction and Wc is the collector width.

82. 发明专利

JPH05333951A 失效
公开(公告)号：JPH05333951A
公开(公告)日：1993-12-17
申请号：JP13922992
申请日：1992-05-29
申请人： TOSHIBA CORP
发明人： TAKASHIMA DAIZABURO , WATANABE SHIGEYOSHI , FUSE TSUNEAKI
IPC分类号： G05F1/56 , G11C11/407 , H01L21/822 , H01L27/04 , H03K19/00
摘要： PURPOSE:To provide a semiconductor integrated circuit device which can reduce the useless power consumption and can generate a desired internal power potential from an external power potential. CONSTITUTION:An lower internal voltage dropping device 3 is selectively connected to a high potential power supply VCC and generates the lower internal power potential VintL. A lower internal circuit 1 works at a potential set between the VCC and potential VintL. An upper internal voltage dropping device 4 is selectively connected to a low potential power supply VSS and generates the upper internal power potential VintU. Then, an upper internal circuit 2 works at a potential set between the VSS and the VintU. In such a constitution, VSS

83. 发明专利

JPH03285352A DYNAMIC TYPE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH03285352A
公开(公告)日：1991-12-16
申请号：JP8294890
申请日：1990-03-31
申请人： TOSHIBA CORP
发明人： WATANABE SHIGEYOSHI , KOYA YOSHITO
IPC分类号： G11C11/404 , H01L27/10 , H01L27/108
摘要： PURPOSE:To reduce in size one layer by employing an SGT structure as not only a memory cell but also an MOS transistor of any region or preferably all regions of a low decoder, a bit line sense amplifier and a peripheral circuit. CONSTITUTION:A memory cell array 1 in which a plurality of word lines and bit lines are crossed and arranged, SGT cells are disposed at the intersections, a low decoder 2 for selecting a word line, a bit line sense amplifier 3 for detecting the data of the bit line, a column decoder 4 for selecting the bit line, an input/output data buffer 5, an address buffer 6 for fetching an external address and clock generators 7, 8 for CAS and RAS systems are formed. Thus, the SGT structure is applied except the array 1 to greatly reduce in size a DRAM chip. If the entire DRAM chip is integrated by the SGT structure, a producing process is simplified as compared with a system in which plane transistors are mixed.

84. 发明专利

JPH02263387A DYNAMIC TYPE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH02263387A
公开(公告)日：1990-10-26
申请号：JP8356589
申请日：1989-03-31
申请人： TOSHIBA CORP
发明人： OTA MASAKO , WATANABE SHIGEYOSHI , OWAKI YUKITO , TSUCHIDA KENJI
IPC分类号： G11C11/401 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To widen the pitch of the upper bit lines and to facilitate the manufacture by providing one line of upper bit line against two lines of bit lines in a multiple bit line system. CONSTITUTION:For instance, a pair of upper bit lines GBL, -GBL connected to a sense amplifier SA become an open bit line system placed on both sides of the sense amplifier SA, and two pieces of bit lines BL1, BL2 being adjacent in a sub-cell array 11 being adjacent to the left of the sense amplifier SA are connected to the upper bit line GBL through selection transistors Q11, Q21 controlled by the same control signal line S1. That is, two pieces of adjacent bit lines of each sub-cell array are connected to one piece of upper bit line through the selection transistor. In such a way, since the pitch of the upper bit lines GBL is widened, working of a wiring layer is facilitated.

85. 发明专利

JPH0294473A NON-VOLATILE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0294473A
公开(公告)日：1990-04-05
申请号：JP24386388
申请日：1988-09-30
申请人： TOSHIBA CORP
发明人： IWATA YOSHIHISA , ITO YASUO , WATANABE SHIGEYOSHI
IPC分类号： H01L21/8247 , G11C11/22 , G11C14/00 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/112 , H01L29/788 , H01L29/792
摘要： PURPOSE:To eliminate the refreshing operation by a method wherein the potential of a capacitor cell plate and the precharged potential are equalized while the whole word lines are connected to a cell transfer gate transistor in case of precharging. CONSTITUTION:During the reading-out process, the whole word lines W2-Wn excluding the word line W1 selected at the time t1 are turned to 0V. The bit line pair B1 and inverted B1 only selected at the time t2 are turned into the floating state. At this time, data are read-out at the word line W1 excluding Vcc+Vth. At the time t3, a sense amplifier 13 is actuated; at the time t4, the bit line pair is set up at 1/2 Vcc; and at the time t5, the whole word lines are set up at Vcc. During the writing-in process, the whole word lines W2-Wn excluding the word line W1 selected at the time T1 are turned to 0V and then word line W1 excluding Vcc+Vth selected at the time t2 is written-in. Finally, at the time t3, the bit line pair is set up at 1/2 Vcc and at the time t4, the whole word lines are set up at Vcc.

86. 发明专利

JPH021129A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH021129A
公开(公告)日：1990-01-05
申请号：JP15818988
申请日：1988-06-28
申请人： TOSHIBA CORP
发明人： SAKUI YASUSHI , HASEGAWA TAKEHIRO , WATANABE SHIGEYOSHI , MASUOKA FUJIO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/08 , H01L27/082 , H01L29/72 , H01L29/732 , H03K3/286 , H03K3/2893 , H03K5/08 , H03K17/60 , H03K19/08 , H03K19/082
摘要： PURPOSE:To obtain a semiconductor device using a bipolar transistor by a method wherein, according to a base potential, a base current can be flowed in a reverse direction in addition to a base current in a forward direction. CONSTITUTION:An N type buried layer 22, an epitaxial silicon layer 23, an N-type well 24 and a field oxide film 25 are formed on the surface of a P type silicon substrate 21. A collector extraction layer 26, a P type base region 27, an N type emitter region 28, an emitter polycide 29 and a P type layer 30 are formed at opening parts; in addition, an N type layer 31 are piled up on the surface of the collector extraction layer 26. This whole assembly is covered with a silicon oxide film 32; a collector electrode, a base electrode and an emitter electrode 35, 36, 37 composed of Al-Si 34 are formed at contact openings via a Ti/TiN film 33. Accordingly, a reverse base current, between the collector and the base, which is larger than a forward base current can flow according to a change in a base potential. Thereby, it is possible to realize a transistor whose base current has a negative region in addition to a conventional positive region.

87. 发明专利

JPH01227297A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH01227297A
公开(公告)日：1989-09-11
申请号：JP5406288
申请日：1988-03-08
申请人： TOSHIBA CORP
发明人： WATANABE SHIGEYOSHI , OWAKI YUKITO , KOBAYASHI TAKAYUKI , SAKUI YASUSHI , ITO YASUO
IPC分类号： G11C11/401 , G11C7/00 , G11C11/34 , G11C11/41
摘要： PURPOSE:To speed up the access of a random access mode by selecting a memory bank near a data output terminal in a DRAM with a serial access function. CONSTITUTION:At the time of a random access, the fall of an RAS is detected and a signal CSF becomes H-level. When the CSF is H-level, a selecting circuit 4 becomes inactive. At the same time, both an ASLT and a BSLT to show which bank is selected become H-level in the selecting circuit 4. The result of this is inputted to an A bank control circuit 2A and a B bank control circuit 2B and column selecting signal lines CSLAj and CSLBj determined by a column address signal other than an Aoc becomes H-level. Thus, memory cell data which are certainly in respective series determined by an address other than the address of bank selection are respectively transferred from the banks 1A and 1B to input/output lines 9A and 9B.

88. 发明专利

JPS63311690A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63311690A
公开(公告)日：1988-12-20
申请号：JP14819187
申请日：1987-06-15
申请人： TOSHIBA CORP
发明人： FUSE TSUNEAKI , NUMATA KENJI , WATANABE SHIGEYOSHI
IPC分类号： G11C11/417 , G11C11/34 , G11C11/409 , G11C11/414
摘要： PURPOSE:To attain high speed readout without malfunction by providing an equalizer between a couple of output nodes of the 1st differential amplifier. CONSTITUTION:In a dynamic RAM where the bit line sense amplifier consists of a CMOS differential amplifier (1st differential amplifier) 4 as a buffer circuit and a BICMOS differential amplifier (2nd differential amplifier) 5 connected to its output node, an equalizer Q11 is provided to short-circuit outputs nodes of the CMOS amplifier in pairs thereby setting the node in equi-potential when the bit line sense amplifier is not selected. Thus, the output node of the CMOS amplifier is set to equi-potential forcibly in the standby state. Thus, the history of the preceding readout cycle is not left, malfunction is prevented and a highly integrated dynamic RAM capable of high speed readout is obtained.

89. 发明专利

JPS63222386A DYNAMIC SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63222386A
公开(公告)日：1988-09-16
申请号：JP5535787
申请日：1987-03-12
申请人： TOSHIBA CORP
发明人： WATANABE SHIGEYOSHI , FUSE TSUNEAKI , SAI YASUSHI
IPC分类号： G11C11/409 , G11C11/34
摘要： PURPOSE:To attain the high speed of a device by inputting the output of a bipolar MOS type differential amplifying circuit to a MOS-FF circuit and restoring. CONSTITUTION:The data of a memory cell 20a and a dummy cell 12a is read to bit lines BL, BL, and a small potential difference is inputted to the base of the driver bipolar transistors T10, T12 of a circuit 56 through a C-MOS current mirror circuit 52a functioning as the impedance element of the bipolar C-MOS differential amplifier 56. Then, the amplified output of the circuit 56 is transferred to output lines OL1, OL2. It is fed back to an FF circuit 54 a through transfer gates FETQ54, Q56 and restored at high speed. Further, the potential difference in the bit lines goes to about 2V, an FF circuit 50a is operated to raise a voltage substantially to a supply voltage. Thereby, the high speed device can be attained.

90. 发明专利

JPS63209220A INVERTER CIRCUIT 失效
公开(公告)号：JPS63209220A
公开(公告)日：1988-08-30
申请号：JP4130487
申请日：1987-02-26
申请人： TOSHIBA CORP
发明人： SAKUI YASUSHI , WATANABE SHIGEYOSHI
IPC分类号： G11C11/407 , G11C11/408 , H01L21/8242 , H01L27/10 , H01L27/108 , H03K19/017 , H03K19/0175 , H03K19/08 , H03K19/0944
摘要： PURPOSE:To attain the output up to a sufficient 'H' level at high speed by composing the titled circuit of one npn transistor and plural (n) channel MOS transistors. CONSTITUTION:When a first input terminal N3 comes to a 'H' level and a second input terminal N5 comes to an 'L' level, first and second MOS transistors Qn1 and Qn2 are turned on, simultaneously, a bipolar transistor T is turned on, second and fourth MOS transistors Qn2 and Qn4 are turned off and the 'H' level is outputted to an output terminal N4. When the output terminal N4 comes to the 'H' level, it rises by the bipolar transistor T at high speed. When the first MOS transistor Qn1 is sufficiently turned on by the coupling between gate sources, the 'H' level is not influenced by the interbase emitter forward direction voltage drop VBE of the bipolar transistor T and rises up to the given pressure rise potential. Thus, a high writing voltage can be obtained.

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