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81. 发明专利

JPH0395795A MULTIPORT MEMORY 失效
公开(公告)号：JPH0395795A
公开(公告)日：1991-04-22
申请号：JP23113089
申请日：1989-09-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HATANO SUSUMU , OOISHI TSURATOKI , KITANO JUN , NISHIMOTO KENJI , NAGASHIMA YASUSHI , KIKUCHI TAKASHI , SAIKOU YASUHIKO , FURUNOMA TOSHIHIKO , SASAKI KOTOKO , UCHIYAMA KUNIO , AOKI HIROKAZU , NISHII OSAMU
IPC分类号： G11C11/41
摘要： PURPOSE:To reduce energy consumption by controlling access operation from an input/output port in one part to a static form and controlling access operation from the remaining input/output port to a dynamic form. CONSTITUTION:A first control circuit 3 to control the access operation through an input/output port 4 in one part to the static form, which always select word lines WL1i and WL2i while following up the change of an input address signal, a second control circuit 7 to control the access operation through a remaining input/output port 8 to the dynamic form which synchronizes the operation to a clock are provided. In a data input/output system to be dynamically interfaced, a current does not flow from a bit line loading element through the selection register of a memory cell 10 and further the driving register of the memory cell 10 normally in a chip selecting state. Thus, the energy consumption can be reduced.

82. 发明专利

JPH0210450A PREFETCH CONTROL SYSTEM FOR CACHE MEMORY 失效
公开(公告)号：JPH0210450A
公开(公告)日：1990-01-16
申请号：JP15912188
申请日：1988-06-29
申请人： HITACHI LTD
发明人： NISHII OSAMU , UCHIYAMA KUNIO , AOKI HIROKAZU , NAGASHIMA YASUSHI
IPC分类号： G06F12/08 , G06F12/12
摘要： PURPOSE:To increase the processing speed of a processor by taking actions of access such as direct increase and repetition into consideration and executing prefetch at the time of profiting from application of prefetch. CONSTITUTION:A processor 10 which controls and executes operation is provided with an instruction decoding part 13 which reads out an instruction to decode the meaning of the instruction and an instruction executing part 19 which executes the instruction in accordance with the decoded results. A cache memory 11 includes an address array 16, a data array 17, and a control logic 19, and the access type of a control logic 19 is detected by a signal which is outputted form the processor 10 and indicates the classification of access, and a prefetch start circuit 24 is started in accordance with the detection result.

83. 发明专利

JPS63225997A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS63225997A
公开(公告)日：1988-09-20
申请号：JP5881087
申请日：1987-03-16
申请人： HITACHI LTD
发明人： NAGASHIMA YASUSHI
IPC分类号： G06F12/02 , G06F12/04 , G11C11/34 , G11C11/401
摘要： PURPOSE:To enable a sector length to be designated and to attach a serial access function, by supplying a sector address and a sector length signal to a multiplication circuit, and performing the access of a memory cell in series via the output signal of the circuit. CONSTITUTION:A readout mode is decided by fetching the sector address SA and the sector length DL by buffers ADB and DLB at a timing when a chip select signal, the inverse of CS changes from an H to an L, and detecting those by a timing control circuit TC when a write enable signal is set at the H. The multiplication circuit AU multiplies the signal SA by the DL, and sends an address signal AY to a shift register SR via a YDCR, and designates a leading address. Also, an address signal AX from the AU is inputted to an XDCR via an ACOUT, and the selection operation of a word line is performed. Next, a readout signal is sent to an FF by a data timing signal phis. The SR starts a shift operation by a clock signal CK, and outputs a data in series from an input/output circuit IOB synchronizing with the CK.

84. 发明专利

JPS63225995A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS63225995A
公开(公告)日：1988-09-20
申请号：JP5880987
申请日：1987-03-16
申请人： HITACHI LTD
发明人： NAGASHIMA YASUSHI , KAJIMOTO TAKESHI
IPC分类号： G11C11/401 , G11C8/04 , G11C11/34
摘要： PURPOSE:To attach a serial access function, by selecting the access of a memory cell corresponding to plural bits setting a sector address as a leading address by synchronizing with a timing signal from the outside. CONSTITUTION:When the readout of 256 bits is performed, a timing control circuit TC generates a data transfer timing signal phis while a sector gap signal is outputted by the output signal SG of a counter circuit CCOUNT and low- order sector address signals A0 and A1. In such a way, a readout signal selected already and responding for the next word line is transferred to an FF. By supplying a signal CK, the readout of the 256 bits corresponding to a 0th sector is enabled by a shift register SR. Also, an address step pulse thetac from the TC performs step of +1, and address signals A2'-A11' for the next word line are outputted, and an XDCR starts the selection operation of the word line corresponding to the next address and the amplification operation of a sense amplifier.

85. 发明专利

JPS63136394A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63136394A
公开(公告)日：1988-06-08
申请号：JP28173386
申请日：1986-11-28
申请人： HITACHI LTD
发明人： NAGASHIMA YASUSHI
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE:To obtain an image memory of optional size without providing external mount components by serially inputting/outputting storage data of a memory cell coupled with a selected word line and data line according to a clock signal supplied externally. CONSTITUTION:The initial value of a row address counter RAC and a pointer PNT are designated via external terminals Ao-Ai at the time of start. The pointer PNT shifts the selection signal written in the bit corresponding to the head column address stored in a column address register CAR according to the serial clock signal SC fed externally. When the word line of the final address is selected by the row address counter RAC, the final row address detection signal raf is formed and the row address counter RAC is initialized again. Thus, the word and data lines starting selection are designated as the head row and column address in the dynamic RAM and the image memory of optional size is constituted.

86. 发明专利

JPS61217990A DYNAMIC TYPE RAM 失效
公开(公告)号：JPS61217990A
公开(公告)日：1986-09-27
申请号：JP5836785
申请日：1985-03-25
申请人： HITACHI LTD
发明人： NAGASHIMA YASUSHI , MIYAZAWA KAZUYUKI , YANAGISAWA KAZUMASA
IPC分类号： G11C11/401 , G11C11/34 , G11C11/407 , G11C11/409
摘要： PURPOSE:To realize two types of writing operation modes and to improve a mass productivity and memory function by identifying a change timing of a write enable signal, and controlling an operation of a data output buffer in referring to a change timing of a column address strobe signal. CONSTITUTION:An internal complementary address signal in accordance with address signals AY0-AYn supplied through an external terminal is formed, and similarly transmitted to a column decoder C-DCR constituted by a static type circuit. The column decoder C-DCR decodes a transmitted address signal and selects a data line by a data line selecting timing signal phiy. A timing control circuit TC receives a low address strobe signal RAS supplied through the external terminal, a column address strobe signal CAS and a write enable signal WE and forms respective types of internal timing signals. Wherein, in order to obtain a variety of an output function of a RAM, in the timing control circuit TC, a timing identifying and controlling circuit is provided.

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