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81. 发明专利

JPS6353711B2 失效
公开(公告)号：JPS6353711B2
公开(公告)日：1988-10-25
申请号：JP6171081
申请日：1981-04-23
申请人： FUJITSU LTD
发明人： MIMURA TAKASHI
IPC分类号： H01L21/20 , H01L21/331 , H01L21/338 , H01L27/088 , H01L27/095 , H01L29/205 , H01L29/73 , H01L29/778 , H01L29/80 , H01L29/812

82. 发明专利

JPS6138854B2 失效
公开(公告)号：JPS6138854B2
公开(公告)日：1986-09-01
申请号：JP11505579
申请日：1979-09-07
申请人： FUJITSU LTD
发明人： MIMURA TAKASHI
IPC分类号： H01L21/306 , H01L21/316 , H01L21/324

83. 发明专利

JPS613465A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS613465A
公开(公告)日：1986-01-09
申请号：JP12375584
申请日：1984-06-18
申请人： FUJITSU LTD
发明人： MIMURA TAKASHI
IPC分类号： H01L29/812 , H01L21/22 , H01L21/338 , H01L27/06 , H01L29/205 , H01L29/43 , H01L29/778 , H01L29/78 , H01L29/80
摘要： PURPOSE:To obtain the title device of high speed and low consumed power by a method wherein the transistor having an n type impurity region and the transistor having a p type impuruty region are connected in cascade by providing the n type and p type impurity regions formed in opposition in a carrier transit layer across a required control layer. CONSTITUTION:When a potential negative from the new of a p type source region 6 is impressed on a control electrode 5, the surface potential of the i type GaAs carrier transit layer 2 decreases, and holes flow in from the source region 6 and are then accumulated in the AlGaAs/i-type GaAs interface, resulting in the induction of a two-dimensional hole channel CP. Electrons can come and go freely between the control electrode 5 and the p type GaAs control layer 4. In other words, in the case of ohmic contact, a depletion layer generates in the interface between an i-type AlGaAs buffer layer 3 and the p type GaAs control layer on the side of this control layer 4, and this layer 4 functions as a control electrode, therefore, a required semiconductor device can be obtained by combining this p-channel semiconductor device and this n-channel semiconductor device.

84. 发明专利

JPS60254657A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60254657A
公开(公告)日：1985-12-16
申请号：JP10943684
申请日：1984-05-31
申请人： FUJITSU LTD
发明人： MIMURA TAKASHI
IPC分类号： H01L29/70 , H01L21/33 , H01L21/331 , H01L29/205 , H01L29/73 , H01L29/737 , H01L29/76
摘要： PURPOSE:To prevent holes from being injected from a base to an emittere by a method wherein the emitter is composed of a semiconductor having an energy band gap larer than that of the semiconductor that forms the base. CONSTITUTION:The base of the titled device has sub-bands E1-En corresponding to minority carriers. When an emitter conductor EC meets the sub-bands E1-En of the base by base-emitter bias, electrons pass through an emitter potential barrier PB E and a collector potential barrier PBC by resonance tunneling. Here, the energy band gap of the emitter semiconductor is made larger than that of the base semiconductor, thereby the injection of holes from the base to the emitter can be prevented.

85. 发明专利

JPS60154667A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS60154667A
公开(公告)日：1985-08-14
申请号：JP1126784
申请日：1984-01-25
申请人： FUJITSU LTD
发明人： MIMURA TAKASHI
IPC分类号： H01L29/205 , H01L29/66
摘要： PURPOSE:To obtain a metal base transistor which has a fast operating velocity by coupling the end of the second semiconductor layer with the first semiconductor layer with a metal layer to become a base, reducing the thickness of the metal base, reducing the contacting area of the metal base with the emitter or collector and reducing the electrostatic capacity therebetween. CONSTITUTION:SiO is radiated and deposited in the direction of an arrow A to form an insulating layer 35 made of the SiO, and a collector offset 36 is performed on the region which approaches the end 33' of Al0.3Ga0.7As layer 33. Then, aluminum for forming a metal base is radiated and deposited in the direction of an arrow B, melted and removed from the unnecessary region, a metal base 37 made of aluminum is formed, and a base offset 37' is performed. Subsequently, an element region is coated with a resist mask 38, O ions are implanted in the direction of an arrow C to the region which surrounds the element region to separate the element, and the emitter 33 and the collector 31 are insulated therebetween. In other words, an insulating region 33'' of shaded broken lines is formed.

86. 发明专利

JPS60113475A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60113475A
公开(公告)日：1985-06-19
申请号：JP22102383
申请日：1983-11-24
申请人： FUJITSU LTD
发明人： MIMURA TAKASHI , KURODA SHIGERU
IPC分类号： H01L29/812 , H01L21/338 , H01L29/41 , H01L29/417 , H01L29/778 , H01L29/80
摘要： PURPOSE:To contrive the speed-up of the titled device by a method wherein a gate electrode is put into ohmic contact with a semiconductor substrate consisting of the first semiconductor layer, a channel layer, and the second semiconductor layer formed by hetero-junction with the semiconductor layer. CONSTITUTION:The non-doped GaAs channel layer 12 is provided with an n type AlGaAs electron supply layer 13, containing a donor impurity, which has a smaller electron affinity than this channel layer and forms a hetero junction with this layer. The rectifying characteristic of the hetero-junction between a source electrode 18 and the channel layer is held by providing this semiconductor substrate with the gate electrode 17 of Schottky contact and the source electrode of ohmic contact.

87. 发明专利

JPS59181060A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS59181060A
公开(公告)日：1984-10-15
申请号：JP5421783
申请日：1983-03-30
申请人： Fujitsu Ltd
发明人： MIMURA TAKASHI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To increase high frequency gain by interposing a base region between upper and lower semiconductor having larger forbidden band width, and forming an energy barrier in the boundary, thereby increasing current gain. CONSTITUTION:The first conductive type semiconductor layer 9 having large forbidden band width is formed on the upper surface of a semiconductor layer 8 having small forbidden band width, and a semiconducltor layer 10 having larger forbidden band width is formed also on the lower surface of the layer 8. The second conductive type semiconductor layer 11 having large forbidden band width is formed at least in contact with the layer 9 on the side of the laminate of the layers 8, 9, 10. Similarly, a semiconductor layer 12 having the second conductive type and large forbidden band width is isolated from the layer 11, and provided in contact with the layer 9. Electrodes 5, 6, 7 are respectively provided on the layers 9, 10, 11, and when they are used as base, emitter and collector electrodes, a current gain is improved, and a lateral hetero junction bipolar transistor having large high frequency gain can be obtained.
摘要翻译：目的：通过在具有较大禁带宽度的上半导体和下半导体之间插入基极区域并在边界中形成能量势垒来增加高频增益，从而增加电流增益。构成：具有较大禁带宽度的半导体层8的上表面形成具有较大禁带宽度的第一导电类型半导体层9，并且还形成具有较大禁带宽度的半导体层10 具有较大禁带宽度的第二导电类型半导体层11至少与层8,9,10的层压体一侧的层9接触。类似地，具有第二导电类型和大的禁带宽度与层11隔离并提供与层9接触。电极5,6,7分别设置在层9,10,11上，并且当它们用作基极，发射极和集电极，电流增益得到改善，并且可以获得具有大的高频增益的横向异质结双极晶体管。

88. 发明专利

JPS59181059A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS59181059A
公开(公告)日：1984-10-15
申请号：JP5421683
申请日：1983-03-30
申请人： Fujitsu Ltd
发明人： MIMURA TAKASHI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72
CPC分类号： H01L29/72
摘要： PURPOSE:To increase the current amplification factor by forming different conductive type emitter and collector from a base region having large forbidden band with at both sides of the base region of small electron affinity formed on a substrate which does not include impurity. CONSTITUTION:A base region 8 made of the same conductive type second semiconductor having smaller electron affinity than the first semiconductor is formed on the first semiconductor layer 7 which does not include impurity, and is interposed between an emitter region 10 and a collector region 11 made of other conductive type semiconductor having larger forbidden band width than the first semiconductor. Electrodes 4, 5, 6 are formed on the regions 8, 9 10. Thus, the operating speed is accelerated, and the current amplification factor can be increased.
摘要翻译：目的：通过在不含杂质的基板上形成的小电子亲和性基底区域的两侧，从具有大禁带的碱性区域形成不同的导电型发射极和集电极来增加电流放大系数。构成：在不包括杂质的第一半导体层7上形成由相同导电类型的第二半导体制成的具有比第一半导体更小的电子亲和力的基极区8，并且介于发射极区10和集电区11之间的具有比第一半导体更大的禁带宽度的其它导电型半导体。电极4,5,6形成在区域8,9,10上。因此，加速了工作速度，可以提高电流放大系数。

89. 发明专利

JPS59124126A Formation of ohmic contact 失效
标题翻译：形成OHMIC联系人
公开(公告)号：JPS59124126A
公开(公告)日：1984-07-18
申请号：JP22925482
申请日：1982-12-29
申请人： Fujitsu Ltd
发明人： MIMURA TAKASHI , KOTANI KOUICHIROU , YAMASHITA YOSHIMI
IPC分类号： H01L29/812 , H01L21/28 , H01L21/338 , H01L29/778
CPC分类号： H01L21/28
摘要： PURPOSE:To obtain contact of low resistance when electrodes to contact ohmically onto a compound semiconductor crystal is to be formed by a method wherein a mask film having electrode contact windows is provided, while the particles of ions, etc., are irradiated to the exposing crystal in the windows to generate damaged regions, and after electrode metals are adhered thereto, the metals are alloyed. CONSTITUTION:An n type GaAs semiconductor layer 2 is grown on a semi-insulating GaAs substrate 1, an SiO2 film 3 to act as a mask is adhered on the whole surface, and contact windows 3A of the plural number are opened in electrode forming regions. Then the particles of ions, neutral atoms, neutral molecules, etc., are implanted into the windows 3A thereof to convert the layer 2 at the parts thereof into semi-insulating layers. Namely, damage is generated to form the damaged regions 5A reduced with carrier concentration. After then, heat treatment is performed for about 1min at about 450 deg.C in an N2 atmosphere, carrier concentration of only the regions 5A is restored to form n type regions 5, an Au.Ge/Au film is adhered on the surfaces of the regions thereof, heat treatment is performed, and the films thereof are alloyed to form electrodes 4, 4'.
摘要翻译：目的：为了通过具有电极接触窗口的掩模膜的方法形成通过欧姆接触的电极到化合物半导体晶体上的低电阻的接触，同时将离子等照射到曝光在窗户中产生晶体以产生损伤区域，并且在电极金属粘附到其上之后，金属被合金化。构成：在半绝缘GaAs衬底1上生长n型GaAs半导体层2，在整个表面上附着作为掩模的SiO 2膜3，并且在电极形成区域中打开多个接触窗口3A 。然后将离子，中性原子，中性分子等的颗粒注入其窗口3A中，以将其部分的层2转化为半绝缘层。即，产生损伤，形成受载体浓度降低的受损区域5A。之后，在N 2气氛中，在约450℃下进行约1分钟的热处理，只有区域5A的载流子浓度恢复形成n +型区域5，Au.Ge/Au膜粘附在其区域的表面进行热处理，并且其膜被合金化以形成电极4,4'。

90. 发明专利

JPS5955073A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5955073A
公开(公告)日：1984-03-29
申请号：JP16614182
申请日：1982-09-24
申请人： Fujitsu Ltd
发明人： KOTANI KOUICHIROU , MIMURA TAKASHI
IPC分类号： H01L29/812 , H01L21/338 , H01L21/8247 , H01L27/06 , H01L29/10 , H01L29/778 , H01L29/788 , H01L29/792 , H01L29/80
CPC分类号： H01L29/1029 , H01L27/0605 , H01L29/7787 , H01L29/80
摘要： PURPOSE: To improve the electron mobility, and the reproducibility of resistivity of source and drain region of the channel layer of a depletion type element by forming a gate electrode for controlling an electron storage layer formed in the vicinity of the first and second semiconductor layers and an N type region selectively arranged at the position corresponding to the gate electrode of the electron storage layer.
CONSTITUTION: A non-doped GaAs layer 12 is formed on a semi-insulating GaAs substrate 11, and a protective film 15 is formed on a semiconductor substrate having an N type AlGaAs layer 13, and an N type GaAs layer 14. Then, impurity ions are implanted to form the channel control region of a depletion type hetero junction field effect element. In order to protect the hetero junction boundary, ion implanted mask employs a laminated structure having a photoresist film 16, a titanium film 17 and a gold film 18. Silicon ions are implanted through the mask, the film 16 is exfoliated and removed, thereby simultaneously removing the films 17, 18. Then, a heat treatment is performed to activate the implanted Si, thereby forming an N type region 20.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过形成用于控制形成在第一和第二半导体层附近的电子存储层的栅电极，提高耗尽型元件的沟道层的源极和漏极区域的电阻率的再现性，以及选择性地配置在与电子存储层的栅电极对应的位置的N型区域。构成：在半绝缘GaAs衬底11上形成非掺杂GaAs层12，在具有N型AlGaAs层13和N型GaAs层14的半导体衬底上形成保护膜15.然后，杂质注入离子以形成耗尽型异质结场效应元件的沟道控制区。为了保护异质结边界，离子注入掩模采用具有光致抗蚀剂膜16，钛膜17和金膜18的层压结构。通过掩模注入硅离子，将膜16剥离并除去，从而同时然后，进行热处理以激活注入的Si，从而形成N型区域20。

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