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81. 发明专利

JPS63186471A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63186471A
公开(公告)日：1988-08-02
申请号：JP1719487
申请日：1987-01-29
申请人： TOSHIBA CORP
发明人： SUGURO KYOICHI , INOUE TOMOYASU
IPC分类号： H01L21/28 , H01L21/225 , H01L21/331 , H01L29/72 , H01L29/73
摘要： PURPOSE:To prevent the decrease of emitter saturation current and base current, make the resistance of a drawing-out lead small, and obtain a uniform and large current amplification factor, by a method wherein a diffusion layer and its electrode are formed at a time, by diffusing impurity mixed previously in a metal into a silicon substrate as the metal is made silicide. CONSTITUTION:An insulating film 14 having an aperture is formed on a silicon layer 13 in which a first conductivity type impurity is introduced. A metal film 15, in which a second conductivity type impurity is mixed, is formed. By heat treatment, the metal film 15 is made silicide, and, along with that, impurity is diffused from the metal film 15 into the above-mentioned silicon layer 18 to form a silicon layer 17 into which a second conductivity type impurity is introduced. For example, an N -Si layer 11 and an N-Si layer 12 are formed on an Si substrate 10, and a P-Si layer 18 is formed by implanting boron ions into the surface of the P-Si layer 12. An oxide film 14 is formed, and a contact hole 14a is made in the oxide film 14. After a W film 15 is formed, As ions are implanted..By heat treatment, a WSi2 film 16 is formed only on Si, and at the same time, an N-Si layer 17 is formed.

82. 发明专利

JP2014187168A Semiconductor device, semiconductor device manufacturing method and semiconductor device manufacturing apparatus 有权
标题翻译：半导体器件，半导体器件制造方法和半导体器件制造设备
公开(公告)号：JP2014187168A
公开(公告)日：2014-10-02
申请号：JP2013060723
申请日：2013-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGURO KYOICHI
IPC分类号： H01L27/105 , C23C14/32 , H01L21/205 , H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/1266 , H01L45/146 , H01L45/1616 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To minimize resistance variation among memory cells and achieve improvement in reproducibility of resistance variation.SOLUTION: According to an embodiment, a semiconductor device comprises a first electrode 24, a second electrode 26 having a metal element and a variable resistive element 25 formed between the first electrode and the second electrode. The variable resistive element includes an insulating first film 25-1 which is formed on the first electrode side and contains O, and a second film 25-2 which is formed on the second electrode side and contains an element having a diffusion coefficient larger than a diffusion coefficient of the metal element in the first film and having electronegativity larger than electronegativity of the metal element.
摘要翻译：要解决的问题：为了最小化存储单元之间的电阻变化并实现电阻变化的再现性的提高。解决方案：根据实施例，半导体器件包括第一电极24，具有金属元件的第二电极26和可变电阻元件 25形成在第一电极和第二电极之间。可变电阻元件包括形成在第一电极侧并且包含O的绝缘的第一膜25-1和形成在第二电极侧上并且包含扩散系数大于的扩散系数的元件的第二膜25-2 金属元素在第一膜中的扩散系数，并且具有大于金属元素的电负性的电负性。

83. 发明专利

JP2012064948A Semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：JP2012064948A
公开(公告)日：2012-03-29
申请号：JP2011209110
申请日：2011-09-26
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO TAKAYUKI , SUGURO KYOICHI
IPC分类号： H01L21/26 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method wich can reduce frequency of wafer destruction due to thermal stress in a ultra high-speed anneal processing.SOLUTION: The semiconductor device manufacturing method comprises a step of irradiating flashlamp light having a pulse width from 0.1 msec to 100 msec on a surface opposite to an auxiliary heated rear face of an auxiliary heated semiconductor substrate to perform thermal processing by using irradiation energy. The step is performed under a reduced-pressure condition such that atmospheric pressure P satisfies the following relation 0.01-0.005(C/W)≤P≤0.4-0.2(C/W)(kgf/cm) where Wrepresents an area of the auxiliary heated rear face of the semiconductor substrate and Crepresents a contact area between the rear face and a susceptor contacting the rear face.
摘要翻译：要解决的问题：提供一种半导体制造方法，其可以在超高速退火处理中降低由于热应力引起的晶片破坏的频率。解决方案：半导体器件制造方法包括在与辅助加热半导体衬底的辅助加热后表面相对的表面上照射具有0.1毫秒至100毫秒的脉冲宽度的闪光灯的步骤，以通过使用辐射进行热处理能源。该步骤在减压条件下进行，使得大气压力P满足以下关系：0.01-0.005（C S / W ）≤P≤0.4-0.2（C S / W S ）（kgf / cm 2 ）其中W S 表示半导体衬底的辅助加热背面的面积，C S 表示背面与接触背面的感受体之间的接触面积。版权所有（C）2012，JPO＆INPIT

84. 发明专利

JP2012019019A Method for manufacturing template and method for manufacturing semiconductor device 有权
标题翻译：制造模板的方法和制造半导体器件的方法
公开(公告)号：JP2012019019A
公开(公告)日：2012-01-26
申请号：JP2010154849
申请日：2010-07-07
申请人： Toshiba Corp , 株式会社東芝
发明人： AZUMA TSUKASA , TOKI TATSUHIKO , SUGURO KYOICHI
IPC分类号： H01L21/027 , B29C33/38 , B29C59/02
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a template reducing failures of a transfer pattern, and a method for manufacturing a semiconductor device.SOLUTION: A method for manufacturing a template of an embodiment includes a step of implanting charged particles at least to a bottom 132a of a recessed part 132 of a template 1. The template 1 has a principal surface 11 on which a pattern 130 having irregularities is formed, and is used in an imprinting process in which the pattern 130 is brought into contact with a resist material 5 formed on a wafer 4 to transfer the pattern 130 to the resist material 5.
摘要翻译：要解决的问题：提供一种减少转印图案故障的模板的制造方法以及半导体装置的制造方法。解决方案：实施例的模板的制造方法包括将带电粒子至少植入模板1的凹部132的底部132a的步骤。模板1具有主表面11，模板130上形成有图案130 形成凹凸，并且用于刻印工艺中，其中图案130与形成在晶片4上的抗蚀剂材料5接触，以将图案130转印到抗蚀剂材料5上。（C） 2012年，JPO＆INPIT

85. 发明专利

JP2012009804A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012009804A
公开(公告)日：2012-01-12
申请号：JP2010243821
申请日：2010-10-29
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUI YUKITERU , MINAMI FUKUGAKU , EDA HAJIME , AMANO MINORU , IWAYAMA MASAYOSHI , YOSHIKAWA MASAHISA , SATO MOTOYUKI , SUGURO KYOICHI , KODERA MASAKO
IPC分类号： H01L27/105 , H01L21/28 , H01L21/304 , H01L21/3205 , H01L21/768 , H01L21/8246 , H01L23/522 , H01L29/82 , H01L43/08 , H01L43/12 , H01L45/00
CPC分类号： H01L21/02697 , H01L21/3212 , H01L21/7684 , H01L21/76877 , H01L21/76883 , H01L27/228
摘要： PROBLEM TO BE SOLVED: To simultaneously achieve high integration of a semiconductor integrated circuit and high performance of a function element.SOLUTION: A semiconductor device comprises: switch elements 3 and 4 disposed on a surface region of a semiconductor substrate 1; a contact plug 6 in which the bottom surface is connected to the switch elements 3 and 4; and a function element 7 disposed directly on the top surface of the contact plug 6. The maximum surface roughness of the top surface of the contact plug 6 is 0.2 nm or less.
摘要翻译：要解决的问题：同时实现半导体集成电路的高集成度和功能元件的高性能。解决方案：半导体器件包括：设置在半导体衬底1的表面区域上的开关元件3和4; 接触插头6，其中底表面连接到开关元件3和4; 以及直接设置在接触插塞6的上表面上的功能元件7.接触插头6的上表面的最大表面粗糙度为0.2nm以下。版权所有（C）2012，JPO＆INPIT

86. 发明专利

JP2009302366A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009302366A
公开(公告)日：2009-12-24
申请号：JP2008156354
申请日：2008-06-16
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGURO KYOICHI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/285 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To prevent metal atoms from being injected into a gate insulating film in forming a gate electrode, and to prevent increase of gate leakage current, destabilization of threshold voltage, and the like.
SOLUTION: This method is used for manufacturing a semiconductor device having an MOS transistor. The gate insulating film 12 is formed on a semiconductor substrate 11. cluster ions 13, each containing a plurality of metal atoms, are deposited on the gate insulating film 12, and at least forms the lowest layer of the gate electrode 14.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了防止在形成栅电极时金属原子被注入到栅极绝缘膜中，并且防止栅极泄漏电流的增加，阈值电压的不稳定等。解决方案：该方法用于制造具有MOS晶体管的半导体器件。栅极绝缘膜12形成在半导体衬底11上，每个含有多个金属原子的簇离子13沉积在栅极绝缘膜12上，并且至少形成栅电极14的最下层。版权所有（C）2010，JPO＆INPIT

87. 发明专利

JP2008124484A Semiconductor device, and method for manufacturing same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008124484A
公开(公告)日：2008-05-29
申请号：JP2007317602
申请日：2007-12-07
申请人： Toshiba Corp , 株式会社東芝
发明人： TSUNASHIMA YOSHITAKA , SUGURO KYOICHI , IINUMA TOSHIHIKO , MATSUO KOJI , MURAKOSHI ATSUSHI
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/336 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To enable miniaturization in a semiconductor in which a gate electrode is manufactured using the damascene gate technology etc. SOLUTION: In the semiconductor device, each gate electrode of an N-type MIS transistor and a P-type MIS transistor is formed via a gate insulating film in a recess formed in a semiconductor substrate, wherein one of the gate electrodes of the N-type MIS transistor and the P-type MIS transistor is configured into a laminated structure of a first metal-containing film F1 and a second metal-containing film F2 on the first metal-containing film and the other gate electrode of the N-type MIS transistor and the P-type MIS transistor is configured into a laminated structure of a third metal-containing film F3 and the second metal-containing film F2 on the third metal-containing film F3. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决方案：使用镶嵌栅极技术等制造栅电极的半导体中的小型化。解决方案：在半导体器件中，N型MIS晶体管的每个栅电极和 P型MIS晶体管通过在半导体衬底中形成的凹部中的栅极绝缘膜形成，其中N型MIS晶体管和P型MIS晶体管的栅电极中的一个被配置为第一在第一含金属膜和N型MIS晶体管和P型MIS晶体管的另一个栅电极上的含金属膜F1和第二含金属膜F2被构造成第三金属膜，在第三含金属膜F3上含有膜F3和第二含金属膜F2。版权所有（C）2008，JPO＆INPIT

88. 发明专利

JP2007220755A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007220755A
公开(公告)日：2007-08-30
申请号：JP2006037107
申请日：2006-02-14
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO TAKAYUKI , SUGURO KYOICHI , MATSUO KOJI
IPC分类号： H01L21/336 , H01L21/265 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823842
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for increasing the density of impurities in a source/drain region and a gate electrode and suppressing a gate leak current, and to provide a manufacturing method of the semiconductor device. SOLUTION: The semiconductor device comprises: a first-conductivity-type semiconductor region 2; second-conductivity-type source and drain regions 9a, 9b for holding one portion of the semiconductor region 2; a second-conductivity-type source extension region 11a that is shallower than the source region 9a between the source region 9a and the semiconductor region 2; a second-conductivity-type drain extension region 11b that is shallower than the drain region 9b between the drain region 9b and the semiconductor region 2; a first gate insulating film 71n on the semiconductor region 2; a second gate insulating film 72n having a nitrogen concentration of 20-57% on the first gate insulating film 71n; and a gate electrode 77n made of a second-conductivity-type semiconductor polycrystalline film on the second gate insulating film 72n. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种用于增加源极/漏极区域和栅极电极中的杂质的密度并抑制栅极漏电流的半导体器件，并提供半导体器件的制造方法。解决方案：半导体器件包括：第一导电型半导体区域2; 用于保持半导体区域2的一部分的第二导电型源极区域和漏极区域9a，9b; 比源极区域9a和半导体区域2之间的源极区域9a浅的第二导电型源极延伸区域11a; 比漏极区域9b和半导体区域2之间的漏极区域9b浅的第二导电型漏极延伸区域11b; 半导体区域2上的第一栅极绝缘膜71n; 在第一栅极绝缘膜71n上具有20-57％的氮浓度的第二栅极绝缘膜72n; 以及在第二栅极绝缘膜72n上由第二导电型半导体多晶膜制成的栅电极77n。版权所有（C）2007，JPO＆INPIT

89. 发明专利

JP2007173743A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007173743A
公开(公告)日：2007-07-05
申请号：JP2005373034
申请日：2005-12-26
申请人： Toshiba Corp , 株式会社東芝
发明人： ITOKAWA HIROSHI , SUGURO KYOICHI , IINUMA TOSHIHIKO , KAWASE YOSHIMASA , AKUTSU HARUKO
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device with which a bonding leak defect can be suppressed.
SOLUTION: A gate electrode 34 is formed on a front face of a semiconductor substrate 10, and a side wall insulation film 41 is formed on a side wall of the gate electrode 34. A metal film is deposited on the semiconductor substrate 10 so as to cover the gate electrode 34 and the side wall insulation film 41, the semiconductor device 10 is placed in atmospheric gases, the metal film is heated by heat conduction of atmospheric gases from front and rear faces of the semiconductor substrate 10, respectively, thereby forming a metal silicide film.
COPYRIGHT: (C)2007,JPO&INPIT

90. 发明专利

JP2007150321A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007150321A
公开(公告)日：2007-06-14
申请号：JP2006324855
申请日：2006-11-30
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGURO KYOICHI , MATSUO KOJI , MURAKOSHI ATSUSHI , SATO YASUHIKO , NIIYAMA HIROMI
IPC分类号： H01L29/78 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device intended to shorten the raw process time (RPT) and improve the machining precision of gate dimensions in a method for manufacturing a semiconductor device using a dummy gate. SOLUTION: The method comprises a process for forming a dummy gate on a semiconductor substrate, a process for forming a source/drain diffusion region by introducing impurities in the semiconductor substrate using the dummy gate as a mask, a process for forming an insulating film around the dummy gate, a process for forming an opening by removing the dummy gate, and a process for forming a gate electrode in the opening via a gate insulating film. The dummy gate is formed by a process for forming a polymer film by applying a polymer whose atomic ratio between carbon and hydrogen (C/H) is one or greater and whose absolute amount of carbon is 50% or greater, that is, a composition in which carbon is excessive, on the semiconductor substrate, a process for forming a photoresist pattern on the polymer film, and a process for transferring the photoresist pattern on the polymer film. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种制造半导体器件的方法，该半导体器件旨在缩短原始处理时间（RPT），并且在使用虚拟栅极的半导体器件的制造方法中提高栅极尺寸的加工精度。解决方案：该方法包括在半导体衬底上形成虚拟栅极的工艺，通过使用伪栅极作为掩模在半导体衬底中引入杂质来形成源极/漏极扩散区域的工艺，在虚拟栅极周围的绝缘膜，通过去除伪栅极形成开口的工艺，以及通过栅极绝缘膜在开口中形成栅电极的工艺。通过将碳与氢原子比（C / H）为1以上且碳绝对量为50％以上的聚合物，即组成其中碳过多，在半导体衬底上，在聚合物膜上形成光致抗蚀剂图案的方法，以及在聚合物膜上转印光致抗蚀剂图案的方法。版权所有（C）2007，JPO＆INPIT

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