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71. 发明专利

JP2689032B2 失效
公开(公告)号：JP2689032B2
公开(公告)日：1997-12-10
申请号：JP7304391
申请日：1991-04-05
IPC分类号： G11C11/408 , G11C5/14 , G11C7/22 , G11C8/18 , G11C11/401 , G11C11/409 , H01L21/822 , H01L27/04 , H01L27/10

72. 发明专利

JPH0955087A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH0955087A
公开(公告)日：1997-02-25
申请号：JP22702195
申请日：1995-08-11
申请人： TEXAS INSTRUMENTS JAPAN , HITACHI LTD
发明人： SAITO TAKESHI , SUKEGAWA SHUNICHI , TACHIBANA TADASHI , SAEKI AKIRA , SUZUKI YUKIE
IPC分类号： G11C11/41 , G11C7/06 , G11C8/18 , G11C11/409
摘要： PROBLEM TO BE SOLVED: To prevent malfunction of a main amplifier and make it properly operate against undesired fluctuation in the level of input address signals. SOLUTION: A main-amplifier activating pulse generator circuit 112' is composed from a response sensitivity reducing circuit 10, a response sensitivity selecting circuit 12, and a main amplifier activating pulse generating section 14. The response sensitivity reducing circuit 10 reduces the response sensitivity or input sensitivity of this circuit 12' for inputted address transition detecting pulse [ATD]. The response sensitivity selecting circuit 12 selects either one of the first and second input terminals A1, A2 in response to the output condition of the pulse generating section 14. Accordingly when the section 14 outputs no main-amplifier activating pulses [MA], the first input terminal A1 (side of the response sensitivity reducing circuit 10) is selected, and otherwise the second input terminal A2 (side of through bypass circuit 11) is selected.

73. 发明专利

JP2531829B2 失效
公开(公告)号：JP2531829B2
公开(公告)日：1996-09-04
申请号：JP11548190
申请日：1990-05-01
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： MATSUI MASAKI
IPC分类号： G11C8/10 , G11C8/18 , G11C11/407 , G11C11/418

74. 发明专利

JP2530055B2 失效
公开(公告)号：JP2530055B2
公开(公告)日：1996-09-04
申请号：JP22866490
申请日：1990-08-30
申请人： TOSHIBA KK , TOSHIBA MAIKUROEREKUTORONIKUSU KK , TOSHIBA JOHO SHISUTEMU KK
发明人： KATO HIDEO , NAKAI HIROTO , IWAHASHI HIROSHI , HIRAGA NOBUAKI
IPC分类号： G11C11/41 , G11C7/02 , G11C7/06 , G11C7/10 , G11C8/18 , G11C11/407 , G11C11/409 , G11C16/06

75. 发明专利

JPH08227598A SEMICONDUCTOR STORAGE DEVICE AND ITS WORD LINE SELECTING METHOD 失效
公开(公告)号：JPH08227598A
公开(公告)日：1996-09-03
申请号：JP3203895
申请日：1995-02-21
申请人： MITSUBISHI ELECTRIC CORP
发明人： NAGASE KOICHI
IPC分类号： G01R31/28 , G11C8/04 , G11C8/18 , G11C11/401 , G11C11/403 , G11C11/406 , G11C29/00 , G11C29/06 , G11C29/14 , G11C29/18 , G11C29/34 , G11C29/50
摘要： PURPOSE: To provide a semiconductor storage device which executes the disturbance test fast and flexibly without being affected by the functions and precision of an external testing device. CONSTITUTION: A disturbance mode control circuit 19 designates the disturbance mode when the address signal of the terminal 8 is at a specified condition at the time of activating a disturbance mode designation signal fed from a control circuit 18 to activate an internal period setting circuit 20. The circuit 20 continuously generates clock signals having a specified period at the time of activation to feed them to the control circuit 18. In compliance with the mode detection signal from this disturbance mode control circuit and the clock signals from the internal period setting circuit, the circuit 18 generates internal address signals in successive synchronization with clock signals from an internal address generation circuit 10 to select the word line of a memory array 7.

76. 发明专利

JP2518810B2 失效
公开(公告)号：JP2518810B2
公开(公告)日：1996-07-31
申请号：JP22310583
申请日：1983-11-29
申请人： FUJITSU LTD
发明人： MYAHARA HATSUO , BABA FUMIO , MOCHIZUKI HIROHIKO
IPC分类号： H03K19/0175 , G11C5/00 , G11C8/18 , G11C11/407 , G11C11/4074 , H03K5/13 , H03K19/00 , H03K19/003 , H03K19/096

77. 发明专利

JPH08506917A 失效
公开(公告)号：JPH08506917A
公开(公告)日：1996-07-23
申请号：JP51836394
申请日：1994-02-10
IPC分类号： G11C17/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/10 , G11C8/18 , G11C16/06 , G11C17/12 , G11C17/18 , H01L21/8246 , H01L27/112 , H01L27/115 , H03K3/3565

78. 发明专利

JPH08147977A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH08147977A
公开(公告)日：1996-06-07
申请号：JP5712695
申请日：1995-03-16
申请人： GOLD STAR ELECTRONICS
发明人： KIN KIYOURITSU , BOKU SHIYOUKUN
IPC分类号： G11C11/41 , G11C7/22 , G11C8/18
摘要： PURPOSE: To obtain a semiconductor memory disabling to write invalid data in a memory cell by using as a signal for pulling up a data line by generating data state transition detection pulse. CONSTITUTION: A data state transition detector 100 inputs a data input signal DIN, detects the state transition of the data, and outputs a data state transition detection pulse DTD0. A data state transition detection pulse composite circuit 200 inputs the pulse DTD0 and the data state transition detection pulses DTS1 to DTSN of other data state transition detector and generates the composite signal DTDSUM of the data transition detection pulse. The signal DTDSUM is input to a NOR gate 22, and used as a signal CIEB for pulling up the data line paired pull-up transistors M6, M7. With the constitution, a write recovery time and data maintaining time can be sufficiently ensured to prevent the input of invalid data.

79. 发明专利

JPH08102185A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH08102185A
公开(公告)日：1996-04-16
申请号：JP23698294
申请日：1994-09-30
申请人： TOSHIBA CORP
发明人： HISADA TOSHIKI , KOINUMA HIROYUKI
IPC分类号： G11C11/41 , G11C8/18 , G11C11/401 , G11C11/407
摘要： PURPOSE: To prevent information stored in a memory cell from being destroyed by noise by controlling the data buffer control circuit through the column address transition detector(CATD) whose threshold value differs depending on the level change condition of the address signal. CONSTITUTION: When noise is generated from the column input buffer 11, and, for example, the column selection lines CSL0, CSL1 are respectively switched to the selection- and non-selection states through the column decoder 14, the on-off operations of the gate 20 are controlled to switch the bit line pairs connected to the data line pairs DQ, BDQ from BL1 and BBL1 to BL0 and BBL0. In this time, the noise level exceeds either threshold value of the CATD 15 whose threshold value differs in response to the level change, the pulse outputted from the CATD 15 causes the regular operation of the data buffer control circuit 17 so that no potential inversion of the bit line pairs BL0, BBL1 occurs and the data of the corresponding memory cell is prevented from being destroyed.

80. 发明专利

JPH0863955A SETTING METHOD OF MODE OF SEMICONDUCTOR MEMORY DEVICE AND CIRCUIT THEREOF 失效
公开(公告)号：JPH0863955A
公开(公告)日：1996-03-08
申请号：JP19141795
申请日：1995-07-27
申请人： SAMSUNG ELECTRONIC
发明人： SAI MEISAN , TEI SEIKIYOKU
IPC分类号： G11C11/401 , G11C7/10 , G11C8/18 , G11C11/407 , G11C11/408
摘要： PROBLEM TO BE SOLVED: To eliminate time loss due to precharge while the operation mode is changed to realize quick operation by generating a mode setting signal in place of a row address strobe signal. SOLUTION: An internal address signal generated by a third logical circuit 54 of an address buffer from an external input address signal AI is supplied to a mode setting circuit from a node N4. This signal is gated with a mode setting control signal WCBREST in the gate means consisting of an NMOS transistor 66 and PMOS transistor 64 and is then latched by inverters 70, 72 and then inverted by an inverter 68 to generate a mode setting signal MDSTi. As explained above, the precharge of the control signal in relation to row address strobe signal/RAS at the time of setting the operation mode change can be eliminated a thereby realizing quick operation by generating the mode setting signal MDSTi independent of the control signal ϕRAS.

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