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71. 发明专利

JP2011254021A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011254021A
公开(公告)日：2011-12-15
申请号：JP2010128196
申请日：2010-06-03
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： HATSUKAWA SATOSHI
IPC分类号： H01L25/07 , G01R31/26 , H01L25/18
CPC分类号： H01L22/10 , H01L22/14 , H01L22/20 , H01L23/24 , H01L24/48 , H01L25/072 , H01L25/50 , H01L2224/4824 , H01L2224/49111 , H01L2224/49175 , H01L2924/00014 , H01L2924/014 , H01L2924/10254 , H01L2924/10272 , H01L2924/1033 , H01L2924/1203 , H01L2924/12042 , H01L2924/1304 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device using small capacity chips.SOLUTION: The method of manufacturing a semiconductor device comprises: a step (S1) of mounting a plurality of SiC semiconductor chips on a mounting board; a step (S2) of applying voltage to the SiC semiconductor chips on the mounting board; a step (S3) of acquiring a temperature distribution image of a surface of the mounting board by a thermal video system such as a thermography or an infrared microscope, with the voltage applied; a step (S5) of judging the presence or absence of a defective chip by performing image analysis; and a step (S7) of rejecting the defective chip by cutting the wiring of the defective chip when there is a defective chip on the mounting board (S5:YES).
摘要翻译：要解决的问题：提供一种使用小容量芯片制造半导体器件的方法。解决方案：制造半导体器件的方法包括：将多个SiC半导体芯片安装在安装板上的步骤（S1）; 向所述安装基板上的所述SiC半导体芯片施加电压的步骤（S2）通过施加电压的方式，通过热像仪或红外显微镜等热像系统来取得安装板的表面的温度分布图像的步骤（S3）通过执行图像分析来判断有缺陷的芯片的存在或不存在的步骤（S5）; 以及当安装板上存在缺陷芯片时，通过切断有缺陷芯片的布线来拒绝有缺陷的芯片的步骤（S7）（S5：是）。版权所有（C）2012，JPO＆INPIT

72. 发明专利

JP2011243916A Semiconductor device, semiconductor unit, and power semiconductor device 有权
标题翻译：半导体器件，半导体器件和功率半导体器件
公开(公告)号：JP2011243916A
公开(公告)日：2011-12-01
申请号：JP2010117219
申请日：2010-05-21
申请人： Toshiba Corp , 株式会社東芝
发明人： TERAMAE SATOSHI
IPC分类号： H01L25/07 , H01L25/18
CPC分类号： H01L25/072 , H01L23/04 , H01L23/049 , H01L23/24 , H01L23/3735 , H01L23/49838 , H01L24/29 , H01L24/32 , H01L24/45 , H01L2224/29101 , H01L2224/32013 , H01L2224/32238 , H01L2224/45124 , H01L2224/83447 , H01L2224/83801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01322 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/15787 , H01L2924/19107 , H01L2924/351 , H05K1/0209 , H05K3/0061 , H05K3/222 , H05K2201/09663 , H05K2201/0969 , H05K2201/1028 , H05K2201/10287 , H01L2924/00 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide means for moderating thermal effect transmitted from a semiconductor element to its peripheral members and preventing degradation of connection reliability of the peripheral members.SOLUTION: A semiconductor device includes: an insulating substrate 10; a first electrode pattern 21 and a second electrode pattern 22 disposed spaced from each other on a first main surface 10a of the insulating substrate 10; a semiconductor element 30 connected to the first electrode pattern 21; an electrode terminal 40 connected to the second electrode pattern 22; and a connection wire 50 that electrically connects the first electrode pattern 21 and the second electrode pattern 22 and has a thermal resistance larger than that of the first electrode 21.
摘要翻译：要解决的问题：提供用于调节从半导体元件向其周边部件传递的热效应的装置，并防止周边部件的连接可靠性的劣化。解决方案：半导体器件包括：绝缘基板10; 在绝缘基板10的第一主表面10a上彼此隔开设置的第一电极图案21和第二电极图案22; 连接到第一电极图案21的半导体元件30; 连接到第二电极图案22的电极端子40; 以及连接线50，其将第一电极图案21和第二电极图案22电连接，并且具有比第一电极21的热阻大的热电阻。（C）2012，JPO＆INPIT

73. 发明专利

JP2011192686A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011192686A
公开(公告)日：2011-09-29
申请号：JP2010055276
申请日：2010-03-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： IKEDA YASUSHI , TOHIRA TOMOTAKE
IPC分类号： H01L21/60
CPC分类号： H01L24/46 , H01L23/24 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/84 , H01L24/85 , H01L25/072 , H01L2224/29111 , H01L2224/32225 , H01L2224/3303 , H01L2224/33181 , H01L2224/37026 , H01L2224/37147 , H01L2224/37655 , H01L2224/40091 , H01L2224/40225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49111 , H01L2224/49505 , H01L2224/73265 , H01L2224/83801 , H01L2224/83805 , H01L2224/84205 , H01L2224/84801 , H01L2224/85 , H01L2224/85205 , H01L2924/00011 , H01L2924/01005 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/20751 , H01L2924/2076 , H01L2924/351 , H01L2924/00014 , H01L2224/78 , H01L2224/29101 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/83205 , H01L2924/01201 , H01L2924/01006
摘要： PROBLEM TO BE SOLVED: To provide a technology of connection wiring on an upper surface of a power semiconductor element having wire bonding with low electrical resistance and high reliability. SOLUTION: A metal conductor (for instance, Cu or a Cu alloy) having a low electrical resistance value and a high linear expansion coefficient is braided into a braided wire, and is connected using a conductive bonding material to a wiring connecting portion on the upper surface of the semiconductor element of the semiconductor device. Thus, strain of the conductive bonding material due to linear expansion of the conductor having the low electrical resistance and the high linear expansion coefficient is suppressed, and both low electrical resistance and high connecting reliability can be achieved. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供具有低电阻和高可靠性的具有引线接合的功率半导体元件的上表面上的连接布线的技术。解决方案：将具有低电阻值和高线性膨胀系数的金属导体（例如Cu或Cu合金）编织到编织线中，并且使用导电接合材料连接到布线连接部分在半导体器件的半导体元件的上表面上。因此，由于具有低电阻和高线性膨胀系数的导体的线性膨胀导致的导电接合材料的应变被抑制，并且可以实现低电阻和高连接可靠性。版权所有（C）2011，JPO＆INPIT

75. 发明专利

JPWO2009081723A1 半導体装置およびその製造方法有权
公开(公告)号：JPWO2009081723A1
公开(公告)日：2011-05-06
申请号：JP2009547019
申请日：2008-12-09
申请人：アイシン・エィ・ダブリュ株式会社 , 富士電機システムズ株式会社
发明人：純司鶴岡 , 純司鶴岡 , 青木　一雄 , 一雄青木 , 正樹小野 , 正樹小野 , 吉原　克彦 , 克彦吉原
IPC分类号： H01L25/07 , B23K26/20 , H01L21/56 , H01L23/48 , H01L25/18
CPC分类号： H01L23/24 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/072 , H01L2224/32225 , H01L2224/371 , H01L2224/3754 , H01L2224/45124 , H01L2224/48091 , H01L2224/4813 , H01L2224/48227 , H01L2224/4846 , H01L2224/4903 , H01L2224/4911 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/12041 , H01L2924/1305 , H01L2924/13055 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/05599 , H01L2224/37099
摘要：レーザ溶接で発生するスパッタが回路パターンや半導体チップに付着するのを防止して、電気的特性の劣化を防ぐことができる半導体装置およびその製造方法を提供する。セラミックス(4)上に形成した銅箔に接続導体(14)をはんだ(13)で固着し、この接続導体(14)の上部面(P)より低く樹脂(17a)を充填してレーザ溶接し、その後で樹脂(17b)を充填することでレーザ溶接で発生するスパッタ(21)が回路パターン(5),(6)や半導体チップ(8)に付着するのを防止する。それによって電気的特性劣化を防止することができる。

77. 发明专利

JP2011023458A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011023458A
公开(公告)日：2011-02-03
申请号：JP2009165619
申请日：2009-07-14
申请人： Toshiba Corp , 株式会社東芝
发明人： TERAMAE SATOSHI
IPC分类号： H01L23/28 , H01L21/56 , H01L25/07 , H01L25/18
CPC分类号： H01L23/24 , H01L23/562 , H01L24/48 , H01L25/072 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device increased in reliability and a method of manufacturing the same. SOLUTION: The semiconductor device 1 is equipped with: a base substrate 10; at least one of semiconductor chips 20a, 20b disposed on the base substrate 10; and a resin case 30 supported on the base substrate 10 while covering the semiconductor chips 20a, 20b. Since partition plates 33af, 33bf for suppressing the growth of a crack 40 generated in the resin case 30 are disposed in the resin case 30, the growth of the crack 40 is checked within a resin member 34B regardless of long-time use of the semiconductor device 1 to maintain the mechanical strength and the appearance of the resin case 30. Thus, the reliability of the semiconductor device 1 is increased. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供可靠性提高的半导体器件及其制造方法。解决方案：半导体器件1配备有：基底10; 设置在基底基板10上的半导体芯片20a，20b中的至少一个; 以及在覆盖半导体芯片20a，20b的同时支撑在基底基板10上的树脂壳体30。由于用于抑制在树脂壳体30中产生的裂纹40的生长的分隔板33af，33bf设置在树脂壳体30中，所以在树脂部件34B内检查裂纹40的生长，而不管长时间使用半导体装置1，以保持树脂壳体30的机械强度和外观。因此，半导体装置1的可靠性增加。版权所有（C）2011，JPO＆INPIT

78. 发明专利

JP2010147453A Manufacturing method of wafer level package 审中-公开
标题翻译：水平包装的制造方法
公开(公告)号：JP2010147453A
公开(公告)日：2010-07-01
申请号：JP2009080137
申请日：2009-03-27
申请人： Samsung Electro-Mechanics Co Ltd , 三星電機株式会社
发明人： KIM JIN GU , KWEON YOUNG DO , JEON HYUNG JIN , PARK SEUNG WOOK , LEE HEE KON , MOON SEON HEE
IPC分类号： H01L23/12
CPC分类号： H01L21/561 , H01L23/24 , H01L23/3121 , H01L24/94 , H01L2924/09701 , H01L2924/181 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a wafer level package. SOLUTION: A manufacturing method of a wafer level package includes a step for preparing a substrate wafer 110 wherein a number of pads 113 are provided to a lower surface, a number of chips 115 are disposed in an upper surface and a dicing line dividing the chip 115 is provided; a step for providing an external connection means 120 to the pad 113; a step for positioning a mask for uncovering the dicing line alone on the substrate wafer 110 and applying resin to the dicing line; a step for removing the mask; a step for capsulation by coating the chip 115 disposed on the substrate wafer 110 with a sealing material 150; a step for removing the resin applied to the dicing line; and a step for discrete dicing by cutting along a dicing line which is exposed by removing the resin. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供晶片级封装的制造方法。解决方案：晶片级封装的制造方法包括制备衬底晶片110的步骤，其中多个焊盘113设置在下表面上，多个芯片115设置在上表面和切割线分配芯片115; 向衬垫113提供外部连接装置120的步骤; 用于定位掩模的步骤，用于在基板晶片110上单独剥离切割线并将树脂施加到切割线; 去除面膜的步骤; 通过用密封材料150涂覆设置在基板晶片110上的芯片115来进行封装的步骤; 去除施加到切割线的树脂的步骤; 以及通过沿着通过去除树脂而暴露的切割线切割而进行离散切割的步骤。版权所有（C）2010，JPO＆INPIT

79. 发明专利

JP2010103519A Package substrate for mounting semiconductor element and method for manufacturing the same 有权
标题翻译：用于安装半导体元件的封装基板及其制造方法
公开(公告)号：JP2010103519A
公开(公告)日：2010-05-06
申请号：JP2009222738
申请日：2009-09-28
申请人： Hitachi Chem Co Ltd , 日立化成工業株式会社
发明人： TAMURA TADASHI , SUGIBAYASHI MANABU , SUZUKI KUNIJI , HATTORI KIYOO
IPC分类号： H05K3/46 , H01L23/12
CPC分类号： H05K1/183 , H01L23/13 , H01L23/24 , H01L23/3121 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H05K3/4611 , H05K3/4623 , H05K3/4697 , H05K2201/09481 , H05K2201/09518 , H05K2201/0959 , H05K2201/10515 , H05K2203/049 , H05K2203/061 , H05K2203/063 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a package substrate for mounting a semiconductor element, which has a high degree of freedom in combining packages and a small limitation in pattern design and makes it possible to connect together a top package and a bottom package at a high density in the case of constituting a PoP, and to provide a method for manufacturing the same. SOLUTION: The package substrate for mounting a semiconductor element includes: a cavity layer which is provided with a cavity material and an adhesive and penetrates them; a base layer laminated on the cavity layer by using the adhesive; a cavity section formed by an opening; and a bottomed via hole formed by a through hole. The cavity layer is provided with an inner layer circuit, a metal coating is formed by plating on the inner wall of the bottomed via hole so as to be bonded to the inner layer circuit, and the bottomed via hole is filled with a conductive resin. The method for manufacturing the same is also provided. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于安装半导体元件的封装基板，其具有组合封装的高自由度和图案设计中的小限制，并且使得可以将顶部封装和底部封装在构成PoP的情况下以高密度，并提供其制造方法。解决方案：用于安装半导体元件的封装基板包括：空腔层，其设置有空腔材料和粘合剂并穿透它们; 通过使用粘合剂层压在空腔层上的基层; 由开口形成的空腔部分; 以及由通孔形成的有底通孔。空腔层设置有内层电路，通过在底层通孔的内壁上电镀形成金属涂层，从而与内层电路接合，底面的通孔填充有导电树脂。还提供了其制造方法。版权所有（C）2010，JPO＆INPIT

80. 发明专利

JP2010103518A Package substrate for mounting semiconductor element and method for manufacturing the same 审中-公开
标题翻译：用于安装半导体元件的封装基板及其制造方法
公开(公告)号：JP2010103518A
公开(公告)日：2010-05-06
申请号：JP2009222737
申请日：2009-09-28
申请人： Hitachi Chem Co Ltd , 日立化成工業株式会社
发明人： TAMURA TADASHI , SUGIBAYASHI MANABU , SUZUKI KUNIJI , MASAKI TAKASHI
IPC分类号： H05K3/46 , H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H05K1/183 , H01L23/24 , H01L23/3121 , H01L23/5384 , H01L23/5389 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06558 , H01L2225/06568 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H05K3/4611 , H05K3/4623 , H05K3/4697 , H05K2201/09481 , H05K2201/09518 , H05K2201/10515 , H05K2203/049 , H05K2203/061 , H05K2203/063 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a package substrate for mounting a semiconductor element, which has a high degree of freedom in combining packages and a small limitation in pattern design and makes it possible to connect together a top package and a bottom package at a high density in the case of constituting a PoP, and to provide a method for manufacturing the same by simple processes at a low cost. SOLUTION: The package substrate for mounting a semiconductor element includes: a cavity layer having an opening and a through hole; a base layer laminated on the cavity layer; a cavity section formed by the opening; and a bottomed via hole formed by the through hole. The package substrate for mounting a semiconductor element has a metal film which is formed by forming a metal coating on the inner wall of the bottomed via hole, filling the bottomed via hole with a conductive resin with the metal coating as a base, arranging a conductive component contained in the conductive resin in an exposed state on the entrance side of the bottomed via hole, and directly depositing plating on the exposed conductive component. The method for manufacturing the same is also provided. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于安装半导体元件的封装基板，其具有组合封装的高自由度和图案设计中的小限制，并且使得可以将顶部封装和底部封装在构成PoP的情况下以高密度，并且通过简单的方法以低成本提供其制造方法。解决方案：用于安装半导体元件的封装基板包括：具有开口和通孔的空腔层; 层叠在空腔层上的基层; 由所述开口形成的空腔部; 以及由通孔形成的有底通孔。用于安装半导体元件的封装基板具有金属膜，该金属膜通过在有底通孔的内壁上形成金属涂层而形成，用带有金属涂层的导电树脂作为基底填充有底通孔，在底部通孔的入口侧处于暴露状态的导电树脂中所含的成分，并且在暴露的导电性部件上直接镀覆电镀。还提供了其制造方法。版权所有（C）2010，JPO＆INPIT

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