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71. 发明专利

JPS5821943A DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPS5821943A
公开(公告)日：1983-02-09
申请号：JP11906781
申请日：1981-07-31
申请人： HITACHI LTD
发明人： HIYAMA KUNIO , KAWAKITA KENJI , TAKADA OSAMU
IPC分类号： H04L12/42 , H04L12/43 , H04L12/437
摘要： PURPOSE:To detect a faulty state, by detecting through at least one node device that the idle/busy display bits of an optional continuous channel are all displayed in the busy state. CONSTITUTION:A frame formation control part 900 stores the frame information that has passed round a loop in a memory 1 within the part 900 by an amount equivalent to a frame via a transmitting/receiving part 400A of a transfer control part. At the same time, the part 900 produces the clock for transmission and produces a pattern of a synchronizing region at first based on said clock. After that, the memory is read to form a frame. Furthermore the part 900 has a function to monitor a fault and then displays forcibly the idle/busy display bit of each channel in an idle state when the state, under which all idle/busy display bits of each channel display the busy state, is continuous more than a certain frequency is detected for both the circuit exchange region and the packet exchange region.

72. 发明专利

JPS5821940A DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPS5821940A
公开(公告)日：1983-02-09
申请号：JP11906481
申请日：1981-07-31
申请人： HITACHI LTD
发明人： HIYAMA KUNIO , KAWAKITA KENJI , TAKADA OSAMU
IPC分类号： G06F13/00 , H04L5/22 , H04L12/43
摘要： PURPOSE:To eliminate the limitation for the processing speed at the terminal device side, by displaying invalidity for the validity display bit of a channel in case the data to be sent in a certain period is not in time when the communication of data is carried out between the communication nodes which are connected to a common signal transmission line. CONSTITUTION:A transmission request signal SREQ is turned on at a terminal device when the transmitting data is completed, and then the transmitting data SD and a transmission request FF516 are set to a transmitting buffer 515. Then the output signal of the FF516 is fed to a transfer controlling part in the form of a validity display bit and along with the data information. When the coincidence of the channel numbers is detected before the transmitting data given from the terminal device is complete, the validity display bit of the data SD becomes zero since the FF516 is reset before the data is transmitted. This shows that the transmitting data is invalid. Accordingly the processing speed is low at the side of the terminal device, and the invalidity is displayed in case the transmitting data is not complete. Thus the terminal device can transmit the data at an optional speed which is lower than a certain period.

73. 发明专利

JPS56118127A DATA TRANSMISSION SYSTEM AND BUS COUPLER 失效
公开(公告)号：JPS56118127A
公开(公告)日：1981-09-17
申请号：JP2050280
申请日：1980-02-22
申请人： HITACHI LTD
发明人： URUGA HIDEO , TAKENOUCHI HIROO , HATADA MINORU , HIYAMA KUNIO
IPC分类号： G06F13/36 , G06F9/52 , G06F13/40 , G06F15/16 , G06F15/173 , G06F15/177
摘要： PURPOSE:To simplify the constitution of the entire system, by making the upper- rank and lower-rank bus couplers with the same circuit constitution. CONSTITUTION:Gates G1, G2, G4 control the transmission signal input to terminals S1, A1, D1 to be output at terminals S2, A2, D2, and the switching of the gates is controlled with the output of a competition control circuit ARB. Gates G3, G5 control the signal for reception inputted to the terminals A2, D2 to be output at the terminals A1, D1, and the on/off of the gates is controlled with the output of comparators CMPL, CMPH. CMPL compares the content of an address setter ASETL with the signal at the terminal A2, and CMPH compares the content of the address setter ASETH with the signal at the terminal A2.

74. 发明专利

JPS55147850A LOOP SYSTEM CONTROLLING SYSTEM 失效
公开(公告)号：JPS55147850A
公开(公告)日：1980-11-18
申请号：JP5573079
申请日：1979-05-09
申请人： HITACHI LTD
发明人： HATADA MINORU , HIYAMA KUNIO , IHARA KOUICHI , IWAI TOKUYUKI
IPC分类号： G06F13/00 , H04L12/437
摘要： PURPOSE:To make it possible to transmit a command signal to all nodes simultaneously, by providing a signal generating circuit, which generates the command signal of a prescribed time width, in each node, in the network system coupled by one-direction loop buses. CONSTITUTION:When command signal (fault signal and so on) V0 of a prescribed time width is generated in node Ni, signal V0 is transmitted to succeeding-stage node Ni+1 and node Ni itself through pulse width shortening circuit 35 and OR gate 34. In case that signal V0 is not generated, the signal from preceding-stage node Ni-1 is transmitted to node Ni itself and succeeding-stage node Ni+1 through AND gate 32 and OR gate 34. Here, if the time width of signal V0 is set to a value larger than the loop one-circulation time, the signal circulated once cannot be taken into node Ni due to the AND gate.

75. 发明专利

JPS55105728A COMPOSITE COMPUTER SYSTEM 失效
公开(公告)号：JPS55105728A
公开(公告)日：1980-08-13
申请号：JP1334579
申请日：1979-02-09
申请人： HITACHI LTD
发明人： URUGA HIDEO , HATADA MINORU , HIYAMA KUNIO , IHARA KOUICHI
IPC分类号： G06F13/36 , G06F3/00 , G06F13/38 , G06F15/16
摘要： PURPOSE:To enable to change the scale and constitution in response to the system requirement flexibly, by providing the common memory, common bus, a plurality of processors, a plurality of memory request circuits corresponding to each processor, and competition prevention unit for the common bus, for each cluster. CONSTITUTION:At least one of a plurality of processors 11a-11n is provided with at least two memory request circuits 12n1, 12n2. The one unit of this fundamental constitution is referred to as cluster. At least one of the two memory request circuits connects the corresponding processor 11n to the bus 13 of the cluster 10 to which the processor 11n belongs, so that the processor 11n can access to the common memory 14 of the cluster 10 to which the processor 11n belongs. The cluster 10 is provided with the memory switch 15 controlling the competition of the bus 13. The constitution in the cluster 20 is entirely the same as that of the cluster 10. As a result, the processor 11n in the cluster 20 can access to the common memory 24 in the cluster 20 as well as the common memory 14.

76. 发明专利

JPS5370367A PACKAGE FOR ELECTRONIC CIRCUIT 失效
公开(公告)号：JPS5370367A
公开(公告)日：1978-06-22
申请号：JP14478776
申请日：1976-12-03
申请人： HITACHI LTD
发明人： DEWA HIROSHI , HIYAMA KUNIO
IPC分类号： H01R12/71 , H01R13/00 , H05K1/11 , H05K3/32 , H05K7/10

77. 发明专利

JPS5336441A TEST AND SETTING SYSTEM 失效
公开(公告)号：JPS5336441A
公开(公告)日：1978-04-04
申请号：JP11080276
申请日：1976-09-17
申请人： HITACHI LTD
发明人： HIYAMA KUNIO
IPC分类号： G06F12/00 , G06F9/52 , G06F15/16 , G06F15/177
摘要： PURPOSE:To facilitate the realization of the test and setting by securing an automatic test and setting function when an access is given to a specified address among the memory addresses of each processor.

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