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71. 发明专利

JPS63273950A DATA PROCESSOR CONTAINING DUPLEX MEMORY 失效
公开(公告)号：JPS63273950A
公开(公告)日：1988-11-11
申请号：JP10892487
申请日：1987-05-06
申请人： FUJITSU LTD
发明人： KAWATO YUTAKA , NARA TAKASHI , HATANO TAKASHI , MORITA SUMIE , FUJIMOTO NAMI
IPC分类号： G06F12/16
摘要： PURPOSE:To realize a high-speed access and to prevent the system breakdown even in case of occurrence of a memory fault by switching a data reading destination to a secondary system-memory from a main system memory when the abnormality of the read data is detected by a check system. CONSTITUTION:When a data error is detected by a parity checker 50, the detection pulses S(g) are sent to latches 50 and 51 from the checker 50. Thus the latch 52 is set and a queuing signal is transmitted via a control line 58. Then a CPU 1 is set under a queuing state. At the same time, the latch 51 is also set and a timing circuit 53 is started by a start signal S(f). The circuit 53 sets a gate circuit 54 into a disable state by a main system bus enable signal S(a) so that the read data given from a main system memory 3 is not sent to the CPU 1. Then a secondary system bus enable signal S(c) is sent to a gate circuit 55 and the circuit 55 is set under an enable state. At the same time, a read pulse S(b) is transmitted and a secondary system memory 4 is read out. Then data are put on a data bus 56 via the circuit 55 and sent to the CPU 1.

72. 发明专利

JPS63105547A DATA TRANSFER REQUEST SYSTEM 失效
公开(公告)号：JPS63105547A
公开(公告)日：1988-05-10
申请号：JP25148986
申请日：1986-10-22
申请人： FUJITSU LTD , FUJITSU DAIICHI TSUSHIN SOFT
发明人： NARA TAKASHI , HATANO TAKASHI , MORITA YOSHIO , MORIYAMA TAKAYUKI , NAKAHARA MINORU
IPC分类号： H04L29/04 , H04L13/00
摘要： PURPOSE:To simplify the processing unit by providing a request transmission means and sending a transmission request of a transmission data outputted from a transmission section and an extracting request of a reception data outputted from a reception section to the processing unit via the same queue. CONSTITUTION:A transmission section 300 applies multiple processing to a transmission data sent in response to the request from the processing unit 100 and sends the result to plural communication lines 200. A reception section 400 applies multiple processing to the reception data reached from the plural communication lines 200 and gives a request of extraction to the processing unit 100. A request transmission means 500 sends the transmission request of a transmission data outputted from the transmission section 300 and the extraction request of the reception data outputted from the reception section 400 to the processing unit 100 via the same queue. Thus, the processing unit 100 has only to supervise the common request transmission means to extract the transmission request of the transmission data to the transmission section 300 and the extraction request of the reception data to the reception section 400 in the order of first-come to the same queue and the supervisory point for the transmission request and the extraction request is unified.

73. 发明专利

JPS6376043A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPS6376043A
公开(公告)日：1988-04-06
申请号：JP22275786
申请日：1986-09-19
申请人： FUJITSU LTD , FUJITSU DAIICHI TSUSHIN SOFT
发明人： NARA TAKASHI , HATANO TAKASHI , KAWATO YUTAKA , SHIOMITSU TSUTOMU , SHIBATA MEGUMI
IPC分类号： G06F13/28
摘要： PURPOSE:To suppress the transfer of invalid data by allowing a direct memory access (DMA) control means receiving a command for temporarily stopping data transfer to stop the continuous transfer of the succeeding data group after ending the transfer of a transferring data group. CONSTITUTION:Receiving a temporary stop command of data transfer from a data transfer stop commanding means 300 in a processor 1 during the continuous transfer of plural data groups 100 by a DMA control means 200, a data transfer stopping means 400 ends the transfer of a transferring data group 100 and then stops the continuous transfer of the succeeding data group 100. Thereby, only the complete data group 100 is transferred before the stop of the transfer. Consequently, all the transferred data are validated and the transfer of invalid data can be suppressed.

74. 发明专利

JPS6320997A ACTIVITY HOLDING SYSTEM FOR DIGITAL SUBSCRIBER'S LINE 失效
公开(公告)号：JPS6320997A
公开(公告)日：1988-01-28
申请号：JP16572686
申请日：1986-07-15
申请人： FUJITSU LTD
发明人： OKADA SUMIE , NARA TAKASHI , HATANO TAKASHI , KAWATO YUTAKA , FUJIMOTO NAMI
IPC分类号： H04Q3/42 , H04L12/02 , H04L12/70
摘要： PURPOSE:To save a power consumption for a customer station equipment by providing a packet monitoring means through a digital subscribers line, and keeping the digital subscriber's line in an active state for a packet communication too, as far as it is under a communication. CONSTITUTION:When a packet information control part 64 detects a monitor frame RR, it inspects whether an activity is set in the packet information control part 64 or not. If the activity is not set, it sets the activity, sends an activity request signal act' and simultaneously starts a clocking by starting a built-in timer circuit 641, and transfers the arrived packet information P to a multiplexing part 62. Further, as the result of the inspection, if the packet information control part 64 judges as the activity is set in it, the timer circuit 641 already being clocking is once initialized and again is started in order to start clocking. Further, the information control part 64 releases the activity being set till then, after the completion of clocking a prescribed time T, and stops to send the activity request signal act' being sent to the multiplexing part 62.

75. 发明专利

JPS62220048A AUTOMATIC RECLAIMING SYSTEM FOR PACKET BUFFER 失效
公开(公告)号：JPS62220048A
公开(公告)日：1987-09-28
申请号：JP6460886
申请日：1986-03-20
申请人： FUJITSU LTD
发明人： HATANO TAKASHI , NARA TAKASHI , KAWATO YUTAKA , KATO MIHARU , OKADA SUMIE
IPC分类号： H04L13/08 , H04L13/00 , H04L29/14
摘要： PURPOSE:To perform a process to transfer data to the same address as at the receiving time of an abnormal packet when receiving a new packet next, by interrupting the transfer of the data, and resetting the address, when the abnormal packet is received. CONSTITUTION:When the operation of the packet is completed abnormally due to a frame check sequence error, etc., an abnormal signal is generated from a packet handling device 1. When receiving the abnormal signal, a transfer circuit 4 interrupts a data transfer. Also, a start pointer 7 is operated by the abnormal signal, and the value in a pointer 5 is returned to the value at the start time of reception of the abnormal packet. Thereby, when a normal packet is received, next, the data is transferred to the same address in a memory 3 as at the transfer time of the abnormal packet at the previous time. Thus, a process for the reclamation of a buffer is performed automatically.

76. 发明专利

JPS62119657A DMA CHAIN CONTROL SYSTEM 失效
公开(公告)号：JPS62119657A
公开(公告)日：1987-05-30
申请号：JP26038285
申请日：1985-11-20
申请人： FUJITSU LTD
发明人： KAWATO YUTAKA , NARA TAKASHI , HATANO TAKASHI , KATO MIHARU , OKADA SUMIE
IPC分类号： G06F13/28 , G06F13/12
摘要： PURPOSE:To add commands with a single and simple procedure independently of the state of a channel to a chained DMA command by providing a final pointer pointing a final discriptor to the channel. CONSTITUTION:The final pointer pointing final discriptors 4-1, 2 is provided to the channel, a new discriptor to be added is prepared, and when processing commanded by a chained discriptor is executed upon the receipt of a notified chain restart command, the chain restart command is neglected, the new discriptor is processed, and when the processing is waiting for the position of the discriptor pointed by the final point register 5, after chain bits 2-1-3 provided in the final discriptor pointed in the final point register are on '1' level, the processing commanded by the discriptor provided newly is controlled for the execution.

77. 发明专利

JPS6259441A COMMUNICATION LINK SUPERVISORY SYSTEM 失效
公开(公告)号：JPS6259441A
公开(公告)日：1987-03-16
申请号：JP19770885
申请日：1985-09-09
申请人： FUJITSU LTD
发明人： KATO MIHARU , NARA TAKASHI , HATANO TAKASHI , KAWATO YUTAKA , OKADA SUMIE
摘要： PURPOSE:To improve the utilizing efficiency of a system by introducing a supervisory protocol sending the transmission of a polling signal from a terminal equipment to a station and executing the supervisory protocol when the polling signal from the station is intermitted for a prescribed time or over. CONSTITUTION:Each counter receives a signal from the station side by a reception circuit 35 via a transmission line 12 and is reset. A counter 31 starts counting and when the number of clocks corresponding to a time T3 is counted, the counter 31 overflows and applies the output of carry C to a signal transmission circuit 37 via an OR gate 36 to send the 1st polling signal S'PL to the station. On the other hand, the C output is fed to the enable terminal of a counter 32 of the next stage to start count. When no signal is received from the station side, the counter 32 overflows, its C output is fed to the circuit 37 via a gate 36 and the 2nd signal S'PL is sent to the station side. When no reaction comes from the station side, the counter 34 overflows to generate an error signal SER, which is sent to the station side via the transmission line 12 and a required error processing is started.

78. 发明专利

JPS61157047A PACKET INFORMATION SUPERVISORY SYSTEM 失效
公开(公告)号：JPS61157047A
公开(公告)日：1986-07-16
申请号：JP27538984
申请日：1984-12-28
申请人： FUJITSU LTD
发明人： KATO MIHARU , NARA TAKASHI , HATANO TAKASHI , KAWATO YUTAKA , OKADA SUMIE
IPC分类号： H04L29/14 , H04L13/00
摘要： PURPOSE:To detect much earlier an abnormality of a data link by decreasing gradually the interval among the 1st inquiry, 2nd and 3rd respectively. CONSTITUTION:A clock CK is given normally to an AND circuit 6. When a data link is established in a layer 2 and a link confirmation inquiry signal is given to an opposite side (terminal side), a data transmission circuit 1 outputs a first a link confirmation inquiry signal signal Q to the terminal side, an AND circuit 6 is set and the clock CK is outputted, then the 1st counter 3 makes count. When the data link is not confirmed normally to the signal Q, the 1st counter 3 outputs a carry C after a time T1 elapsed, the circuit 1 outputs the Q and the 2nd counter 4 is activated. In case of an abnormality, no replay signal is returned even to the signal Q at the 2nd time, a counter 4 outputs a carry after a time T2 elapsed and the data transmission circuit 1 output the signal Q and a counter 5 is activated.

79. 发明专利

JPS60142698A DIGITAL SIGNAL TRANSMISSION METHOD 失效
公开(公告)号：JPS60142698A
公开(公告)日：1985-07-27
申请号：JP24770383
申请日：1983-12-29
申请人： FUJITSU LTD
发明人： HATANO TAKASHI , NARA TAKASHI , KAWATO YUTAKA , OKADA SUMIE
IPC分类号： H04Q11/04
摘要： PURPOSE:To enhance application efficiency of a transmission wire by multiplying a group of multiple-system outslot signals and by trasmitting the signal group to a digital network after adjusting the signal speed to a speed of an inslot signal. CONSTITUTION:An inslot signal BI of 64Kb/s which is a sound signal from multiple function terminals 22-1-22-4, is directly connected to a digital network 24, whereas an outslot signal DO of 16Kb/s which is a data signal is multiplied by a multiplying device 25 for four subscriber shares and sent out to the network 24 as a multiple outslot signal S. A multiplied outslot signal sent out from the network 24 is separated by a dividing device 26 and distributed to subscriber circuits 23-1-23-4 by a dividing device 27 based on packet addresses.

80. 发明专利

JPS58205359A Digital multi-frequency receiving system 失效
标题翻译：数字多频接收系统
公开(公告)号：JPS58205359A
公开(公告)日：1983-11-30
申请号：JP8825682
申请日：1982-05-25
申请人： Fujitsu Ltd
发明人： HATANO TAKASHI , OGAWA YASUNORI , TANAKA YASUO , SHIMOZONO RIYOUJI , SEKI YOUKO
IPC分类号： H04L27/26
CPC分类号： H04L27/26
摘要： PURPOSE:To detect the point of time of signal stop quickly, by obtaining a total power of sound and signals and detecting the point of time of stop of receiving signals with this total power, in a device detecting the signals transmitted on the same communication channel with the sound. CONSTITUTION:The sound and signals incoming to an input terminal 1 are applied to a signal detecting circuit 2, a sound detecting circuit and a power detecting circuit 6 at the same time. Each detected output of the circuits 2, 3, 6 is applied to a signal discriminating circuit 4 to detect the presence of the signals. In this case, the signal detecting circuit 2 is a circuit using the discrete Fourier transformation, where the point of time of signal stop is detected with a delay. A signal discriminating circuit 4 detects the point of time of signal stop with the stop of an output of the power detecting circuit 6 when the output of the signal detecting circuit exists and decreases the output of the signal detecting circuit 2.
摘要翻译：目的：为了快速检测信号停止时间，通过获得声音和信号的总功率，并以该总功率检测接收信号的停止时间点，在检测在相同通信信道上发送的信号的设备中与声音。构成：输入到输入端子1的声音和信号同时被施加到信号检测电路2，声音检测电路和功率检测电路6。电路2,3,6的每个检测的输出被施加到信号鉴别电路4以检测信号的存在。在这种情况下，信号检测电路2是使用离散傅里叶变换的电路，其中以延迟检测信号停止的时间点。信号鉴别电路4在信号检测电路的输出存在时停止功率检测电路6的输出，并且信号检测电路2的输出减小，来检测信号停止的时间点。

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