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61. 发明专利

JPS57154610A DIGITAL MODULATING AND DEMODULATING SYSTEM 失效
公开(公告)号：JPS57154610A
公开(公告)日：1982-09-24
申请号：JP4068681
申请日：1981-03-20
申请人： GEN CORP
发明人： KURITA NAOSABUROU , SHINOHARA TATSUOKI
IPC分类号： H03M5/12 , G11B20/10 , G11B20/14 , H03M5/16 , H03M7/14 , H04L25/49
摘要： PURPOSE:To record data with a high density, by reducing a maximum interval of magnetization inversion to facilitate clock regeneration by using a specific pattern instead of a preceding code word when a prescribed bit of the code word based on the 3PM system is 0. CONSTITUTION:In case of the modulation of a data signal based on the 3PM system, when all bits from the second bit P2 to the sixth bit P6 of a code word M are 0 and the first bit P1 and the second bit P2 of a next code word N are 0, pattern 001001 is used as a code word instead of the code word M. In case of the demodulation of the code word subjected to 3PM modulation, pattern 001001 is demodulated to the same data word as 100000 in parallel with the demodulation of data signals based on the 3PM system. For example, a 3PM modulating circuit (a) and a 3PM demodulating circuit (b) shown in firgures are used to perform digital magnetic recording and reproducing in this manner.

62. 发明专利

JPS5731330B2 失效
公开(公告)号：JPS5731330B2
公开(公告)日：1982-07-03
申请号：JP13231373
申请日：1973-11-26
IPC分类号： H03M5/16 , H03M5/18 , H04L7/00 , H04L25/49

63. 发明专利

JPS5792944A TRANSMITTING DEVICE 失效
公开(公告)号：JPS5792944A
公开(公告)日：1982-06-09
申请号：JP16867480
申请日：1980-11-29
申请人： TOHO SEISAKUJIYO KK
发明人： NAKAMURA TADAHIKO , HIGUCHI TATSUO
IPC分类号： H03M5/16 , H04L7/00 , H04L7/04
摘要： PURPOSE:To prevent the rise and the fall of a synchronizing pulse from dulling, by adding an auxiliary pulse of the opposite polarity continuously at the rise of the fall of the synchronizing pulse and transmitting them in case that the synchronizing pulse of the positive or negative polarity is transmitted. CONSTITUTION:An output P1 of an oscillator Aa is applied to an input terminal I of a counter Ab. The counter Ab divides the output P1 to generate a pulse P2 for modulation from an output terminal Qa. A signal S1 (0,1-n) is generated from an output terminal Ob. A control circuit Ad generates a control signal S2 in accordance with the signal S1 to control a data generating circuit Ac. The data generating circuit Ac generates a reset pulse P30 and an auxiliary pulse P'30 of the polarity opposite to that of the pulse P30 continuously. Further, count pulses P31-P3n and auxiliary pulses P'31-P'3n of the polarity opposite to that of these count pulses are generated continously. The reset pulse P30 and the auxiliary pulse P'30 are applied to a reset terminal R of the counter Ab. Data D1-D16 are inputted to a modulating circuit Ae and are outputted to a transmission line L as time division data signals D1'-D16'.

64. 实用新型

JPS5762462U JPS5762462U - 失效
公开(公告)号：JPS5762462U
公开(公告)日：1982-04-13
申请号：JP13804480
申请日：1980-09-30
IPC分类号： H03M5/16 , H03K5/00 , H03K5/08 , H03M5/18 , H04L25/03 , H04L25/49

65. 发明专利

JPS5744351A Code error detecting circuit 失效
标题翻译：代码错误检测电路
公开(公告)号：JPS5744351A
公开(公告)日：1982-03-12
申请号：JP11840380
申请日：1980-08-29
申请人： Fujitsu Ltd
发明人： HIDA NORIYUKI , FUJIMOTO NAONOBU
IPC分类号： H03M5/16 , H03M13/00 , H04L1/24 , H04L25/49
CPC分类号： H04L1/247
摘要： PURPOSE:To simplify the circuit constitution of a code error detecting circuit for HDBn codes, by monitoring digital integral values of the HDBn codes by using a universal shift register. CONSTITUTION:The principal part of an error detecting circuit which detects errors of HDBn (High Density Bipolar n) codes used by a digital transmission system consists of two stages of universal shift registers and two AND gates 22 and 24. The universal shift registers 20 are capable of transferring data to left and right and this operation is utilized to monitor digital integral values of HDBn codes. An HDBn code free from a code error never has >=3 successive pulses of the same polarity, so the largest digital integral value of the HDBn is 2 and when the digital integral value exceeds two, the code is regarded as an error.
摘要翻译：目的：为了简化HDBn码的码错误检测电路的电路结构，通过使用通用移位寄存器监视HDBn码的数字积分值。构成：检测由数字传输系统使用的HDBn（高密度双极性n）码的误差的误差检测电路的主要部分由两级通用移位寄存器和两个与门22和24组成。通用移位寄存器20为能够将数据传输到左和右，并且该操作被用于监视HDBn码的数字积分值。没有代码错误的HDBn代码从不具有相同极性的> = 3个连续脉冲，因此HDBn的最大数字积分值为2，当数字积分值超过2时，该代码被认为是错误。

66. 实用新型

JPS572752U 失效
公开(公告)号：JPS572752U
公开(公告)日：1982-01-08
申请号：JP7865580
申请日：1980-06-06
IPC分类号： H03M5/04 , H03M5/16 , H04L25/49 , H04B9/00

67. 发明专利

JPS56125142A IDENTIFIED REPRODUCTION CIRCUIT 失效
公开(公告)号：JPS56125142A
公开(公告)日：1981-10-01
申请号：JP2852280
申请日：1980-03-06
申请人： NIPPON ELECTRIC CO
发明人： KOBAYASHI KOUICHI
IPC分类号： H03M5/16 , H04L25/03 , H04L25/24 , H04L25/49 , H04L25/52
摘要： PURPOSE:To simplify constitution and to reduce the power consumption, by the identified reproduction through the use of a positive and a reverse clock signals for tri-state data, in an identified reproduction circuit for an input signal used for PCM relay device, etc. CONSTITUTION:The identified reproduction circuit of tri-state data consists of an identification circuit 5, gate circuit 6 and FFs 7, 8, and the positive and reverse data (a), (b) obtained from the input data are given to input terminals 9, 10, and clock signal C is input to terminal 17. The gate circuit 6 forms positive and reverse timing signals C, g from the clock signal C, the identified circuit 5 compares the data (a), (b) with the threshold value VR in positive phase timing. If the positive data is greater than the threshold value, the positive identification signal (d) is output, and if both the data are smaller than the threshold value, the zero identification signal (f) is output, and if both data are smaller than the threshold value, the zero identification signal (f) is output and it is fed to FFs 7, 8, and FF8 outputs the zero identification signal (h) during the reverse timing, and the positive reproduction signal (i) is output from the terminal 18 of FF7 and the negative reproduction signal (j) is output from the terminal 19.

68. 发明专利

JPS56117458A SIGNAL TRANSMITTING DEVICE 失效
公开(公告)号：JPS56117458A
公开(公告)日：1981-09-14
申请号：JP2178180
申请日：1980-02-22
申请人： MITSUBISHI ELECTRIC CORP
发明人： CHIBA KAZUHIRO
IPC分类号： H03M5/16 , H03M7/06 , H04L25/49 , H04N1/413
摘要： PURPOSE:To realize a reproduction of the signal faithful to the transmission signal, by converting the signal of the demodulated trigonometric function waveform into a triangular waveform and reproducing the triangular waveform into a binary signal. CONSTITUTION:The characters and pictures to be transmitted are converted into the binary digital signals through a photoelectric converting circuit and then into the ternary digital signals by a binary-ternary converting circuit. Furthermore the ternary signals receive a band limitation through a band limiting filter and are modulated by a modulator circuit to be transmitted to the transmission line. The signal transmitted via the transmission line is reproduced by the demodulator circuit 15; and the trigonometric function waveform d5 is transmitted and then converted into the signal f5 of a triangular waveform through the waveform limiting circuit 21. The signal f5 is converted into the binary signal e5 through the ternary-binary converting circuit 16. Then the signal e5 is changed into a hard copy by the recording circuit 17 to reproduce the characters and pictures.

69. 发明专利

JPS5690659A PROTECTING CIRCUIT FOR BIPOLAR VIOLATION 失效
公开(公告)号：JPS5690659A
公开(公告)日：1981-07-22
申请号：JP16723179
申请日：1979-12-22
申请人： FUJITSU LTD
发明人： SHINODA RIYOUICHI , SUDOU MAKOTO , HASHIMOTO KENICHI , TAKEUCHI HIROYUKI
IPC分类号： H03M5/16 , H04L1/24 , H04L7/00 , H04L7/04 , H04L7/08 , H04L25/49
摘要： PURPOSE:To protect bipolar violation by a simple circuit by utilizing the regularity of the bipolar violation. CONSTITUTION:Bipolar violation information (a) is sent to shift register 32 via inverter 31 and shifted successively with clock (b). To gate 35, only outputs 39 and 31 among outputs of register 32 are connected via inverters 33 and 34 and 1/8 counter 36 divides the frequency of clock (b) by eight at any time, so that even if information (a) has disturbance, a correct output can be obtained from terminal (d).

70. 发明专利

JPS5632858A ERROR DISCRIMINATION CORRECTION SYSTEM OF BIPOLAR SIGNAL RECEIVER 失效
公开(公告)号：JPS5632858A
公开(公告)日：1981-04-02
申请号：JP10860379
申请日：1979-08-28
申请人： NIPPON ELECTRIC CO
发明人： KOYAMA TOORU
IPC分类号： H03M5/16 , H04L1/24 , H04L25/08
摘要： PURPOSE:To make it possible for a simple circuit to discriminate a received bipolar signal with accuracy, by correcting error discrimination due to an influence of the hump of a ternary discriminating circuit. CONSTITUTION:Between ternary discriminating circuit 6 and bipolar decoder 7 in bipolar signal receiver 10, correcting circuit 8 is interposed. As a result, adder 81 adds the output signal of ternary discriminating circuit 6 to a signal obtained by inverting a correction output signal which is previously delayed by one-bit delay circuit 82 and precedes by one time slot, thereby obtaining the correction output signal. Therefore, a bipolar signal, passed through the transmission line, which has the same polarity with the main pulse of the bipolar signal and is accompanied by an echo of greaqer amplitude than the absolute value of the threshold level of the ternary discriminating circuit 6 can accurately be discriminated one time slot after the main pulse of the bipolar signal.

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