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61. 发明专利

JP2001156073A METHOD FOR PREVENTING COPPER CONTAMINATION ON SIDE WALL OF VIA OR DUAL DAMASCENE STRUCTURE 失效
公开(公告)号：JP2001156073A
公开(公告)日：2001-06-08
申请号：JP2000234284
申请日：2000-08-02
申请人： CHARTERED SEMICONDUCTOR MFG
发明人： GUPTA SUBHASH , HO KWOK KEUNG PAUL , ZHOU MEI-SHENG , CHOOI SIMON
IPC分类号： H01L21/302 , H01L21/304 , H01L21/306 , H01L21/3065 , H01L21/3205 , H01L21/768 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a method for avoiding contamination in copper metallization upon manufacturing an integrated circuit. SOLUTION: Copper contamination on an inter-metal dielectric layer in via or dual damascene etching is prevented by forming a lid layer on the first copper metallization. The first copper metallization is formed in the dielectric layer on a semiconductor substrate, where a barrier metallic layer is formed under the first copper metallization and above the dielectric layer. The first copper metallization is flattened and then etched to form a recess below the surface of the dielectric layer. A conductive lid layer is deposited on the first metallization within the recess or on the dielectric layer. The conductive lid layer is removed by using one of several methods to remove the upper part of the first copper metallization within the recess.

62. 发明专利

JP2001044151A CARRIER HEAD FOR CHEMICAL MECHANICAL POLISHING 失效
公开(公告)号：JP2001044151A
公开(公告)日：2001-02-16
申请号：JP2000120246
申请日：2000-04-21
申请人： CHARTERED SEMICONDUCTOR MFG
发明人： SEBASTIAN SAA WII KUUKU
IPC分类号： B24B37/32 , H01L21/304 , B24B37/00 , B24B37/04
摘要： PROBLEM TO BE SOLVED: To provide a carrier head which improves uniformity of pressure of a semiconductor wafer with respect to polishing pad during chemical mechanical (CMP) polishing operation. SOLUTION: This carrier head uses independent adjustment screws 58, threaded into a carrier 48 to uniformize the pressure of a wafer and prolong the service life of a guide ring 50. The adjustment screws are threaded inwardly so that a support plate receives holder screws mounted to the guide ring, thereby easily changing a spacing between the carrier and guide ring with the adjustment screws. A gas is maintained by rotation stopper units 56 of the adjustment screws.

63. 发明专利

JP2000347417A ALIGNMENT POST OBTAINED BY PHOTOLITHOGRAPHY METHOD, DEVICE STRUCTURE OF LIQUID CRYSTAL DISPLAY PROVIDED WITH OPTICAL INTERFERENCE LAYER AND ITS FORMATION 失效
公开(公告)号：JP2000347417A
公开(公告)日：2000-12-15
申请号：JP2000060761
申请日：2000-03-06
申请人： CHARTERED SEMICONDUCTOR MFG
发明人： SUU YON JII , RAVI SANKAA YARAMANCHI , HAN CHII GYANGU
IPC分类号： G02B1/11 , G02F1/1335 , G02F1/1339 , G02F1/136 , G02F1/1362 , G03F7/20 , G09F9/00
摘要： PROBLEM TO BE SOLVED: To obtain a new method for forming an insulating material-made alignment post associated with an active element structure by forming a silicon wafer provided with active elements having patterns on the inside and outside and adhering the insulating material-made alignment post onto each pattern of the active element structure to form a pattern. SOLUTION: A transparent encircled body is obtained using a glass cover plate 10 to return light incident from the outside on a viewer by reflecting the light. The intensity of the reflected light is controlled by electric fields generated in liquid crystalline materials 11. An IC chip 12 separated from the glass plate by interposing an alignment post 14 generates such electric fields. The space formed as the result between the glass plate and the silicon wafer is filled with the selected liquid crystalline materials 11. Any of the supplied light and the light from the circumference is penetrated into the opened face of the liquid crystal on the silicon wafer and reflected on pixels disposed downward to form a polarized visible pattern.

64. 发明专利

JP2000323710A FABRICATION OF LOW OVERLAP CAPACITANCE INTEGRATED CIRCUIT 失效
公开(公告)号：JP2000323710A
公开(公告)日：2000-11-24
申请号：JP2000106267
申请日：2000-04-07
申请人： CHARTERED SEMICONDUCTOR MFG
发明人： PAN YANG , AAJUAN RYU
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/51 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To reduce the gate-drain overlap capacity of a MOS transistor on a semiconductor device by forming a local region of low permittivity oxide in a gate-drain overlap region. SOLUTION: A low permittivity gate oxide layer 6 of 20-200Åthick is formed by CVD similar to that employed in post-process or spin-on method. The low permittivity gate oxide layer 6 may also be formed of a thermal oxide layer and injected with fluorine in order to decrease permittivity of the thermal oxide. Energy level being employed for injecting fluorine is in the range of 20-80 keV. Fluorine injection is normally followed by rapid thermal anneal process, i.e., RTA process. Representative value of permittivity attained through the low permittivity providing process is in the range of 2-3.5.

65. 发明专利

JP2000299293A METHOD FOR FORMING CONDUCTIVE CONTACT IN SEMICONDUCTOR DEVICE BY DUAL DAMASCENE METHOD 失效
公开(公告)号：JP2000299293A
公开(公告)日：2000-10-24
申请号：JP2000079807
申请日：2000-03-22
申请人： CHARTERED SEMICONDUCTOR MFG
发明人： CHOI PEN SHII , WAI BUUN ROO , RAP CHAN
IPC分类号： H01L21/28 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/312 , H01L21/316 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To form a via contact while planarizing an excess metal layer without forming any recess by depositing a conductive metal in an opening made through first and second deposited insulation layers, depositing a third insulation layer and further making an opening, and then depositing a plasma polymerized methyl silane layer thereby forming an oxide thereof. SOLUTION: An insulation layer 4 is formed on the insulation layer 3 of a semiconductor substrate 2 and an opening is made therein before a conductive metal is deposited in the insulation layer 4. Furthermore, an insulation layer 8 is deposited and an opening is made above a conductive metal line 6 and a layer of photosensitive polymer, i.e., plasma polymerized methyl silane(PPMS), is deposited. Subsequently, it is exposed to UV-ray to form a plasma polymerized methyl silane oxide(PMSO) 14. Thereafter, a barrier conductive layer lining the region of trench and via is deposited followed by deposition of a conductive metal layer such that the layer acts as a diffusion barrier and CMP etch stop thus planarizing an excess metal layer 28 by CMP without forming any recess of metal.

66. 发明专利

JP2000174058A MANUFACTURE OF INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000174058A
公开(公告)日：2000-06-23
申请号：JP25738299
申请日：1999-09-10
申请人： CHARTERED SEMICONDUCTOR MFG
发明人： WONG GEORGE
IPC分类号： G02F1/1345 , G02F1/1362 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To optimize the thicknesses of pixels and bonding pads by patterning a metal line and bonding pads on a first metal layer deposited on an insulating layer, and depositing a dielectric layer, second and third metal layers, and a passivation layer thereon, and thereafter forming conducting openings passing through the dielectric layer and the passivation layer. SOLUTION: An insulating layer 18 is formed on a semiconductor substrate 10, and a first metal layer is deposited on the layer 18. The first metal layer is patterned, thereby forming a metal line 20 and bonding pads. An intermetallic dielectric layer 24 is deposited thereon, and a second metal layer is formed to fill the layer 24. The second metal layer is etched, thereby forming tungsten plugs 38 on metallic lines 30 and 32. Further, a third metal layer is deposited on the layer 24 and the plugs 38 and thereafter patterned. Pixels 42 that are in contact with the plugs 38 are formed, and after depositing a passivation layer thereon, conducting openings are formed in part thereof.

67. 发明专利

JP2007059912A Ic stress control system 审中-公开
标题翻译： IC应力控制系统
公开(公告)号：JP2007059912A
公开(公告)日：2007-03-08
申请号：JP2006226613
申请日：2006-08-23
申请人： Chartered Semiconductor Mfg Ltd , チャータード・セミコンダクター・マニュファクチャリング・リミテッド
发明人： LEE JAE GON , CHUA CHER SIAN , ANG CHEW HOE , HSIA LIANG CHOO
IPC分类号： H01L21/8238 , H01L27/08 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7842
摘要： PROBLEM TO BE SOLVED: To provide an IC stress control system capable of employing a shallow trench isolation portion so that PMOS device performance may be raised without deteriorating NMOS device performance.
SOLUTION: First, a gate (108) is formed on a substrate (106). Then, a channel (112) is formed on the substrate (106). Next, a source/drain (118) is formed around the gate (108). After that, a shallow trench isolation portion (132) is formed on the substrate (106), and the shallow trench isolation portion (132) produces a distortion on the channel (112). Finally, a stress suppression structure (134) is formed on the substrate (106).
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够采用浅沟槽隔离部分的IC应力控制系统，使得可以在不劣化NMOS器件性能的情况下提高PMOS器件性能。解决方案：首先，在基板（106）上形成栅极（108）。然后，在基板（106）上形成通道（112）。接下来，在栅极（108）周围形成源极/漏极（118）。之后，在衬底（106）上形成浅沟槽隔离部分（132），并且浅沟槽隔离部分（132）在通道（112）上产生失真。最后，在衬底（106）上形成应力抑制结构（134）。版权所有（C）2007，JPO＆INPIT

68. 发明专利

JP2006119651A Method for fabricating phase shift mask, and phase shift mask 审中-公开
标题翻译：用于制作相位移屏蔽的方法和相位移屏蔽
公开(公告)号：JP2006119651A
公开(公告)日：2006-05-11
申请号：JP2005306747
申请日：2005-10-21
申请人： Chartered Semiconductor Mfg Ltd , チャータード・セミコンダクター・マニュファクチャリング・リミテッド
发明人： TAN SIA KIM , LIN QUNYING , HSIA LIANG-CHOO
IPC分类号： G03F1/08 , H01L21/027
CPC分类号： G03F1/30
摘要： PROBLEM TO BE SOLVED: To provide a method (1100) for fabricating a phase shift mask (104).
SOLUTION: A trenched phase shift mask (104) having portions of a light-blocking layer (206) thereon is formed (1102). A layer (802) comprising an anti-reflective material is formed on the trenched phase shift mask (104) and the portions of the light-blocking layer (206) (1104). The anti-reflective material (802) is then removed on horizontal surfaces of the trenched phase shift mask (104) and of the portions of the light-blocking layer (206).
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于制造相移掩模（104）的方法（1100）。解决方案：形成其上具有遮光层（206）的部分的沟槽相移掩模（104）（1102）。包括抗反射材料的层（802）形成在沟槽相移掩模（104）和遮光层（206）（1104）的部分上。然后在沟槽相移掩模（104）和遮光层（206）的部分的水平表面上去除抗反射材料（802）。版权所有（C）2006，JPO＆NCIPI

69. 发明专利

JP2004274021A Method of manufacturing three-dimensional metal-insulator-metal capacitor for dynamic random access memory(dram) and ferroelectric random access memory(feram) 审中-公开
公开(公告)号：JP2004274021A
公开(公告)日：2004-09-30
申请号：JP2003339500
申请日：2003-09-30
申请人： Chartered Semiconductor Mfg Ltd , チャータード・セミコンダクター・マニュファクチャリング・リミテッド
发明人： CHENG WEI-HUA , YEN DANIEL , TAKAHASHI KUNIHIKO , LEI MING , JOY THOMAS
IPC分类号： H01L20060101 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115
CPC分类号： H01L21/76895 , H01L27/10855 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a metal-insulator-metal(MIM) capacitor provided with an insulator having a high dielectric constant or a ferroelectric interelectrode film conformable to a double damascene modus.
SOLUTION: A method of integrating the MIM by the double damascene modus comprises the steps of: forming a first plane insulating layer 20 and depositing an etching stop layer 22 and a second insulating layer 24; etching a capacitor node contacts opening 1 against a substrate; and etching a first recess 2 against the etching stop layer 22. A conductive layer 26 is filled in the contacts opening and the first recess by using the double damascene modus. A second recess 3 is formed around the capacitor node contacts on the second insulating layer. A first conformation metal layer 28, an interelectrode dielectric layer 30 and a second metal layer 32 are deposited and simultaneously patterned to form a capacitor upward the node contacts. The second recess increases a capacitor area, while patterning the metal layer, resulting in decreased treatment step.
COPYRIGHT: (C)2004,JPO&NCIPI

70. 发明专利

JP2004266243A Test structure for on-chip real-time reliability testing 审中-公开
公开(公告)号：JP2004266243A
公开(公告)日：2004-09-24
申请号：JP2003318386
申请日：2003-09-10
申请人： Chartered Semiconductor Mfg Ltd , チャータード・セミコンダクター・マニュファクチャリング・リミテッド
发明人： MANNA INDRAJIT , FOO LO KENG , QIANG GUO , XU ZENG
IPC分类号： G01R31/12 , G01R31/26 , G01R31/28 , G01R31/30 , H01L21/66 , H01L23/544
CPC分类号： G01R31/2858 , G01R31/129 , G01R31/2642 , G01R31/2884 , G01R31/3004 , H01L22/34
摘要： PROBLEM TO BE SOLVED: To reduce down time of a system in which an IC is used, by taking out an end-of-life flag before failure occurrs in an active IC.
SOLUTION: A system with three on-chip monitoring test structures is used. A first test structure (10) monitors hot carrier degradation. A second test structure (30) monitors TDDB degradation. A third test structure (50) monitors electromigration degradation. Each of these test structures (10, 30 and 50) has logical output level. The logical output level indicates a time at which the test structure has judged that the IC has reached end-of-life. When one of the test structures outputs the end-of-life logical level, an end-of-life indicator (70) outputs a logical level showing that failure will soon occur in the IC so that it is to be exchanged.
COPYRIGHT: (C)2004,JPO&NCIPI

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