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    • 62. 发明专利
    • MULTIPLE-DATA-BASE RETRIEVAL DEVICE
    • JPH0991309A
    • 1997-04-04
    • JP25040295
    • 1995-09-28
    • TOSHIBA CORP
    • MANABE TOSHIHIKOTAKAHASHI KAZUSHIGESUMITA KAZUO
    • G06F17/30
    • PROBLEM TO BE SOLVED: To perform retrieval from multiple data bases on the basis of an array of words without paying attention to a schemer by generating a retrieval command according to a selected concept dictionary and performing retrieval from a data base according to the generated retrieval command. SOLUTION: A concept dictionary selection part 11 determines a concept dictionary to be retrieved according to a vocabulary that is being inquired. A relation determination part 12 determines the relation between words according to the concept dictionary of the selected data base. A retrieval command generation part 13 converts the array of vocabularies into a retrieval command according to the relation between the words. This retrieval command is executed by a retrieval command execution part 14. A retrieval command execution part 14 requests a data base management system which manages element data bases to execute the command as the conversion result, thereby performing retrieval. Its retrieval result is displayed at a retrieval result display part 15.
    • 64. 发明专利
    • VECTOR ADDRESS GENERATION SYSTEM
    • JPH03123967A
    • 1991-05-27
    • JP26028189
    • 1989-10-06
    • TOSHIBA CORP
    • INOUE ATSUSHIMANABE TOSHIHIKOIWASA SHIGEAKI
    • G06F17/16
    • PURPOSE:To simplify hardware by realizing an address register as the register having the number of bits, which is smaller than the bit width of memory space and using a computing element having the number of bits, which is smaller than the bit width of memory space. CONSTITUTION:The base address register 1 storing a vector base address VA is realized as the register of 32 bits since an address VA is given as data of 32 bits which absolutely designates the address space of the bit width. On the other hand, an incremental register 2, an index register 3, a step register 4 and a vector number register 5 are realized as the registers of 16 bits. A first multiplier 6 is constituted of the multiplier of 16 bits since an input is 16 bits. A second multiplier 7 which multiplication-processes the output of the multiplier 6 is realized as the multiplier of 16 bits. Since an adder 8 addition-processes data of 32 bits, which is stored in the register 1, and the values of 16 bits, which are obtained in the multipliers 6 and 7, it is therefore constituted by 32 bits.
    • 65. 发明专利
    • ADDRESS GENERATING DEVICE
    • JPH01284965A
    • 1989-11-16
    • JP11534088
    • 1988-05-12
    • TOSHIBA CORP
    • MANABE TOSHIHIKO
    • G06F17/16
    • PURPOSE:To simultaneously utilize an index without executing the collection and dispersion of vector data by dispersing an index memory to plural banks and simultaneously and parallelly reading the bank. CONSTITUTION:An index memory 100 is composed of four banks 101-104 of #0-#3 and these banks are determined by address low order to bits. Reading control is composed of an arbiter 111, a bank selector 112, address registers 113-116 and selectors 117-119. The arbiter 111 inputs plural index addresses IADi based on a requesting signal REQi which goes to be '1' at the read requesting time of the index. Then, when bank collision is generated from the value of these index addresses IADi, the index address IADi, in which the collision is generated, is arbitrated. The bank selector 112 selects the bank to be accessed in correspondence to the value of the low order 2 bits in the index address IADi after the arbitration and the bank is read from the index memory 100.
    • 66. 发明专利
    • PRODUCING DEVICE FOR CIRCUIT DIAGRAM
    • JPS63195772A
    • 1988-08-12
    • JP2731387
    • 1987-02-10
    • TOSHIBA CORP
    • MANABE TOSHIHIKO
    • G06F17/50
    • PURPOSE:To attain the effective use of a space and to produce a fine-looking picture by calculating the number of section areas based on the size of each circuit symbol of the size of uniform divided areas and arranging the circuit symbols according to said number of section areas. CONSTITUTION:A connection information memory part 15 stores the types of circuit elements and connection information on an AND gate, an inverter, etc. A symbol area memory part 16 stores the sizes of circuit symbols and a section size memory part 17 stores the sizes of section areas. While a section number calculating part 12 calculates the number of sections of each circuit symbol to supply them to an arrangement processing part 11, calculates a section range occupied by each circuit symbol and produces arrangement information based on the connection information supplied from the part 15 so that each circuit symbol is set at each optimum position on a picture. Thus it is possible to avoid such a space wasting problem where just one small circuit like an AND circuit, etc., is set in a large section area where a flip-flop can be provided.
    • 67. 发明专利
    • PROGRAM BRANCH CONTROLLER
    • JPS62190532A
    • 1987-08-20
    • JP3183486
    • 1986-02-18
    • TOSHIBA CORP
    • NISHIO SEIICHIMANABE TOSHIHIKO
    • G06F9/32
    • PURPOSE:To reduce the capacity of a program to improve the execution efficiency by comparing an operation result with plural optional values simultaneously and deciding states of comparison results to determine whether the control is branched or not. CONSTITUTION:An operating circuit 120 calculates values on signal lines 131 and 132 and outputs the result onto a signal line 135. A comparing circuit 123 compares the calculation result with the value of a register 121, and signal lines 141-143 are set to '1', '0', and '0' at the time of the operation result is larger, and these signal lines are set to '0', '1', and '0' at the time of they are equal to each other, and these signal lines are set to '0', '0', and '1' at the time of the operation result is smaller. A comparing circuit 124 compares the calculation result with the value of a register 122 similarly, and signal lines 144-146 are set to '1', '0', and '0' at the time of the operation result is larger, and these signal lines are set to '0', '1', and '0' at the time of they are equal other, and these signal lines are set to '0', '0', and '1' at the time of the operation result is smaller. A discriminating circuit 125 generates information, which indicates whether a branch condition is satisfied or not, based on bit of information indicating the state of comparison results sent through signal lines 141-146 and that sent through a signal line 151 which should be tested, and this information is sent to a branch control circuit 126, which controls branch of the program actually, through a signal line 160.