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61. 发明专利

JPH07161989A SEMICONDUCTOR DEVICE MANUFACTURING METHOD 失效
公开(公告)号：JPH07161989A
公开(公告)日：1995-06-23
申请号：JP30924593
申请日：1993-12-09
申请人： TOSHIBA CORP
发明人： AOKI NOBUTOSHI
IPC分类号： H01L29/78
摘要： PURPOSE:To manufacture a MOS suitable for miniaturization with excellent controllability by a method wherein the diffusion of impurities when a gate insulator film is formed and the evaporation of impurities from a substrate surface are reduced. CONSTITUTION:This method includes a step of forming a first insulator film 4a on the surface of a semiconductor substrate 1; a step of implanting ions into the semiconductor substrate 1 through the first insulator film 4; and a step of forming a second insulator film 4b between the first insulator film 4a and the semiconductor substrate 1. Thus, it is possible to reduce the impurity diffusion when a gate insulator film is formed or the evaporation of impurities fro the substrate, and to form a thin high concentration layer, and to manufacture a MOS suitable for miniaturization with excellent controllability.

62. 发明专利

JPH06290240A SIMULATION METHOD 失效
公开(公告)号：JPH06290240A
公开(公告)日：1994-10-18
申请号：JP7393993
申请日：1993-03-31
申请人： TOSHIBA CORP
发明人： AOKI NOBUTOSHI , NAKAMURA MITSUTOSHI
IPC分类号： G06F17/50 , H01L21/00 , G06F15/60
摘要： PURPOSE:To provide the simulation method which evades troublesome initializing at the time of simulation and eliminates an unnecessary calculation area. CONSTITUTION:This method includes steps 103 and 104 for determining a 2nd area extending in the depth direction of ion injection or in the lateral direction from an impurity distribution function determined from a range, dispersion, and high-order moment or an impurity distribution found by a simulator dedicated to ion injection or by measuring an ion injection profile and a step 105 for expanding or reducing a 1st calculation area on the basis of the 2nd area for ion injection simulation in the 1st calculation area. Even a user who is not proficient in the simulation can initialize a proper calculation area and perform the simulation precisely at a high speed.

63. 发明专利

JP2003163347A SIMULATOR AND SIMULATING METHOD 审中-公开
公开(公告)号：JP2003163347A
公开(公告)日：2003-06-06
申请号：JP2001362629
申请日：2001-11-28
申请人： TOSHIBA CORP
发明人： KUSUNOKI NAOKI , AOKI NOBUTOSHI
IPC分类号： G01R31/28 , G06F17/50 , H01L21/336 , H01L21/66 , H01L29/00 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a simulator in which the effect of stress, or the like, onto the characteristics of an element can be evaluated quantitatively. SOLUTION: The simulator for evaluating the characteristics of a semiconductor device comprises a first calculating section for calculating a first value corresponding to a specified physical value for at least a partial region of the semiconductor device while taking account of a specified physical quantity, a second calculating section for calculating a second value corresponding to a physical value for at least a partial region of the semiconductor device without taking account of a physical quantity, and a visualizing section for displaying correlation of the first and second values in a specified form. COPYRIGHT: (C)2003,JPO

64. 发明专利

JP2002141409A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
公开(公告)号：JP2002141409A
公开(公告)日：2002-05-17
申请号：JP2000333811
申请日：2000-10-31
申请人： TOSHIBA CORP
发明人： YAEGASHI TOSHITAKE , AOKI NOBUTOSHI
IPC分类号： H01L21/76 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device suppressed with the decline in the impurity density of a diffusion region due to various heat treatments near the interface between an element isolation region and an element formation region. SOLUTION: The semiconductor device comprises a semiconductor substrate 1; a plurality of element formation regions 12 which are disposed on the semiconductor substrate 1 and are to be formed with semiconductor elements; the element isolation region formed by embedding an oxide film 10 in part of the semiconductor substrate 1 to isolate the element formation regions 12 from each other; and an oxide nitride film 9 disposed on the interface between the element formation regions 12 and the element isolation region. On the interface between the element formation regions 12 where the semiconductor elements are to be formed and the element isolation region embedded with the oxide film 10, the oxide nitride film 9 is disposed. The diffusion of impurities in the oxide nitride film 9 is smaller than that in the oxide film 10.

65. 发明专利

JPH10335193A MANUFACTURING PROCESS SPECIFICATION GENERATION/OPERATION SYSTEM, PROCESS DATA GENERATION SYSTEM, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10335193A
公开(公告)日：1998-12-18
申请号：JP15608497
申请日：1997-05-30
申请人： TOSHIBA CORP
发明人： AOKI NOBUTOSHI , KANEMURA TAKANAGA
IPC分类号： B23Q41/08 , B65G61/00 , G05B17/02 , G05B19/418 , G06F19/00 , G06Q50/00 , G06Q50/04 , H01L21/00 , H01L21/02 , G06F17/60
摘要： PROBLEM TO BE SOLVED: To provide a manufacture process specification/operation system, wherein simulation is effectively used by using a process data which can be inputted in both a production control system and a simulation system. SOLUTION: This system comprises a production control system 2, wherein an instruction is issued to a manufacturing device, used in each process of manufacturing process, or the manufacturing device is controlled, a simulation system 3 which performs a simulation for each process of the manufacturing process, and a process data generation system 1 provided with a storage device, in which a process data which can be used as an input data for both the production control system 2 and the simulation system 3 and an compilation device for compiling the process data. A simulation is effectively used for product development, and technical know-hows regarding product manufacturing and a know-how for simulation are easily made into a database collectively.

66. 发明专利

JPH10125612A SIMULATION METHOD 失效
公开(公告)号：JPH10125612A
公开(公告)日：1998-05-15
申请号：JP28245696
申请日：1996-10-24
申请人： TOSHIBA CORP
发明人： AMAKAWA HIROTAKA , NAKAMURA MITSUTOSHI , AOKI NOBUTOSHI
IPC分类号： H01L21/22 , H01L21/00 , H01L21/265
摘要： PROBLEM TO BE SOLVED: To obtain analysis of high precision in a narrow calculation region by setting the boundary condition of a region for simulation, in such a manner that impurities or point defect move across the boundary of the calculation region. SOLUTION: Diffusion time T is set to 0 (S 101). By calculating the diffusion. coefficients or the like at a diffusion temperature, a diffusion equation is set (S 102). The boundary of the simulation region, i.e., the boundary condition to a substrate bottom surface is so set, that it is allowed for impurities or point defects to exceed the boundary of the calculation region and move (S 103). After the boundary condition and the diffusion equation are set, analysis of the diffusion equation is obtained by using a numerical analysis method (S 104) Next, the diffusion time T is increased by ΔT (S 105). Whether the value excess the total diffusion time Tf is judged (S 106). When it exceeds Tf, the loop which starts from the setting of the diffusion equation is again executed.

67. 发明专利

JPH05291518A 失效
公开(公告)号：JPH05291518A
公开(公告)日：1993-11-05
申请号：JP8879992
申请日：1992-04-09
申请人： TOSHIBA CORP
发明人： AOKI NOBUTOSHI
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/784
摘要： PURPOSE:To form a MOS-FET which has a small occupying area and sufficient channel length and channel width to manufacture a C-MOS transistor by a method wherein two types of vertical transistors are formed in parallel with each other and the trench circumferences of the transistors are used as active region. CONSTITUTION:A P-type well 3 and an N-type well 4 are vertically formed in a P-type semiconductor substrate 1 in parallel with each other. A trench lying across both the wells 3 and 4 is formed and a first insulator layer 5, conductive layer 6 and a second insulator layer 20 are built up on the bottom of the trench. Then a trench which lies across the first trench and the wells 3 and 4 are formed and n-type ions such as arsenic ions are implanted to form conductive layers 7a, 7b and 8c and, further, p-type ions such as boron ions are implanted to form the conductive layers 8a, 8b and 7c. Then a trench reaching the conductive layer 6 is formed in the second insulator 20 and the trench is filled with metal or silicide to for a conductive layer. Successively, contact holes are formed in an insulator layer 24 which is formed over the whole surface and electrodes 12-17 which are connected to a gate electrode and respective layers are formed to complete a C-MOS device.

68. 发明专利

JP2006351626A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2006351626A
公开(公告)日：2006-12-28
申请号：JP2005172667
申请日：2005-06-13
申请人： TOSHIBA CORP
发明人： KATO KOICHI , MATSUSHITA DAISUKE , MURAOKA KOICHI , NAKASAKI YASUSHI , MITANI YUICHIRO , AOKI NOBUTOSHI
IPC分类号： H01L21/28 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a gate electrode containing boron on a gate insulation film containing nitrogen, is very reliable and has stable characteristics, and also to provide its manufacturing method. SOLUTION: The semiconductor device 100 comprises a semiconductor substrate 10, the insulation film 20 formed on the semiconductor substrate, and the electrode 30 which is formed on the insulation film and contains boron and a semiconductor material. Either a group V element or carbon, or a combination of two or more elements selected among group V elements or carbon is introduced into the interface 40 between the insulation film and the electrode. COPYRIGHT: (C)2007,JPO&INPIT

69. 发明专利

JP2000150669A SEMICONDUCTOR INTEGRATED CIRCUIT AND FABRICATION THEREOF 失效
公开(公告)号：JP2000150669A
公开(公告)日：2000-05-30
申请号：JP32697398
申请日：1998-11-17
申请人： TOSHIBA CORP
发明人： AOKI NOBUTOSHI , OUCHI KAZUYA , MIZUSHIMA ICHIRO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/80
摘要： PROBLEM TO BE SOLVED: To obtain a stabilized threshold level by forming the first region of a gate electrode of first and second group IV elements of different kind and forming a second region of the first group IV element thereby preventing impurities doped into the gate electrode from leaking to the channel region side. SOLUTION: A gate electrode 4P, 4N has a first underlying region 4g formed on the gate insulation film 3 side contiguously thereto, and an second overlying region 4p, 4n formed on the first region 4g while spaced apart from the gate insulation film 3. The first region 4g is formed of SiGe having a group IV element, i.e., Si, and a different group IV element, i.e., Ge. The second region 4p, 4n is formed of one kind of group IV element, i.e. Si. In a complementary MISFET of dual gate electrode structure, the threshold voltages can be stabilized respectively using identical gate electrodes 4P, 4N containing first and second group IV elements.

70. 发明专利

JPH0922877A SIMULATION DEVICE AND ITS METHOD 失效
公开(公告)号：JPH0922877A
公开(公告)日：1997-01-21
申请号：JP17093495
申请日：1995-07-06
申请人： TOSHIBA CORP
发明人： AOKI NOBUTOSHI , KANEMURA TAKANAGA
IPC分类号： H01L21/22 , G06F17/00 , G06F19/00 , G06Q50/00 , G06Q50/04 , H01L21/00
摘要： PROBLEM TO BE SOLVED: To enhance the efficiency of semiconductor element design by providing a storage part which stores a local reaction parameter determination module or a cohesion potential parameter determination module and a processing part which simulates the activation concentration or diffusion of impurities including semiconductor elements. SOLUTION: An operator sends a command to execute a simulation through an input part. This command is inputted into a processing part through an input/output control part. The processing part recognizes the command from the operator and copies a simulation execution file to a main memory part therein. Further, the processing part executes a local reaction parameter determination module to determine a parameter of reaction between the impurity and point defect, or a cohesion potential parameter determination module to determine a potential which characterizes the cohesion of impurity is Thus, the effect such as cohesion of impurity, reduction of activation thereof due to diffusion is effectively adopted to simulation, resulting in highly improved calculation accuracy.

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