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61. 发明专利

JP2005252335A Integrated circuit device and manufacturing method thereof 有权
标题翻译：集成电路设备及其制造方法
公开(公告)号：JP2005252335A
公开(公告)日：2005-09-15
申请号：JP2004055956
申请日：2004-03-01
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIGASHIYA HIDEKI , SHIMAMURA TETSUO
IPC分类号： H01L23/12 , H03H3/08 , H03H9/25
CPC分类号： H01L24/94 , H01L2924/14 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit device having stable characteristics and capable of forming a micro and lightweight integrated circuit device with a large-scale wafer process, and a manufacturing method thereof.
SOLUTION: A space is formed on an electronic component element by a cover 14 and spacers 13. With this configuration, electronic characteristics of a surface acoustic wave electronic element etc. can be protected from being changed due to physical contact to the outside and stabilizing the characteristics, and a simple connection structure with conductive bumps 12 can improve simulation accuracy of high-frequency characteristics. As a result, the design of the integrated circuit device can be simplified. Also, electromagnetic shielding can be performed for the electronic component element and a leading-out wiring, and the characteristics can be stabilized.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有稳定特性并能够形成具有大规模晶片工艺的微型和轻型集成电路器件的集成电路器件及其制造方法。解决方案：通过盖14和间隔件13在电子元件上形成空间。通过这种构造，可以保护表面声波电子元件等的电子特性不会由于与外部的物理接触而改变并且稳定特性，并且具有导电凸块12的简单连接结构可以提高高频特性的模拟精度。结果，可以简化集成电路器件的设计。此外，可以对电子元件和引出布线进行电磁屏蔽，并且可以使特性稳定。版权所有（C）2005，JPO＆NCIPI

62. 发明专利

JP2005150448A Circuit substrate and its manufacturing method 审中-公开
标题翻译：电路基板及其制造方法
公开(公告)号：JP2005150448A
公开(公告)日：2005-06-09
申请号：JP2003386647
申请日：2003-11-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SUGAWA TOSHIO , HIGASHIYA HIDEKI , IDA HIDEJI
IPC分类号： H05K3/40 , H05K3/18 , H05K3/22 , H05K3/38
摘要： PROBLEM TO BE SOLVED: To provide a circuit substrate and its manufacturing method in which a conductor resistance can be reduced, a fine pattern in a widthwise direction can be formed, and also a peel-off strength is large.
SOLUTION: In the circuit substrate, a wiring pattern 112 composed of a coarse layer 107, a conductive layer 108 and a conductive layer 111 is embedded from a face of the coarse layer 107 onto at least one face of an insulating substrate 101 in which a conductive material 106 is filled in a through hole 105, and an insulating material 113 is filled in between the wiring patterns 112. Separately from the insulating substrate 101, the insulating material 113 is filled in between the wiring patterns 112, and a deformation or inclination caused by an external mechanical stress of the wiring pattern 112 is reduced, and additionally a fine adjustment for an amount of the insulating material 113 of the insulating substrate 101 is unwanted. A coefficient of expansion is made close to that of the wiring pattern 112 by mixing fine particles of metal oxide, etc., a stress due to a temperature is relieved, and a thermal conduction is improved, thereby making such an adjustment as to enhance an efficiency of heat radiation, etc.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题为了提供可以降低导体电阻的电路基板及其制造方法，可以形成沿宽度方向的精细图案，并且剥离强度也大。解决方案：在电路基板中，将由粗糙层107，导电层108和导电层111构成的布线图案112从粗糙层107的表面埋入绝缘基板101的至少一个面上其中导电材料106填充在通孔105中，并且绝缘材料113填充在布线图案112之间。与绝缘基板101分开地，绝缘材料113填充在布线图案112之间，并且由布线图案112的外部机械应力引起的变形或倾斜减小，另外对绝缘基板101的绝缘材料113的量进行微调。通过混合细小的金属氧化物等的细微的膨胀系数使得膨胀系数接近于布线图案112的膨胀系数，减轻由于温度导致的应力，提高热传导，从而进行这样的调整热辐射效率等。版权所有（C）2005，JPO＆NCIPI

63. 发明专利

JP2005005684A Multilayer board and manufacturing method therefor 审中-公开
标题翻译：多层板及其制造方法
公开(公告)号：JP2005005684A
公开(公告)日：2005-01-06
申请号：JP2004137648
申请日：2004-05-06
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAYA YASUHIRO , HIGASHIYA HIDEKI , NAKAMURA SADASHI , ECHIGO FUMIO
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayer board and a manufacturing method therefor, which obtain stable electric connection by sufficiently compressing a conductive paste at the time of hot pressing and allow a thermosetting resin to be charged into spaces between wiring patterns in inner layers without leaving any gap.
SOLUTION: A multilayer board (215) has multiple wiring substrates (206 and 210) that are laminated. At least one wiring substrate (210) located outside has holes which penetrate through the substrate in the thickness direction. A conductive material (209) is charged into the holes and is cured. The multiple wiring substrates (206 and 210) have wiring layers (211') that are electrically connected through the cured conductive material (209). The wiring layers (211'), which are positioned outside the cured conductive material (209), protrude outside the surrounding areas.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种多层板及其制造方法，其通过在热压时充分压缩导电膏而获得稳定的电连接，并且使热固性树脂充电到布线图案之间的空间中内层而不留任何间隙。解决方案：多层板（215）具有层叠的多个布线基板（206和210）。位于外侧的至少一个布线基板（210）具有在厚度方向上贯穿基板的孔。将导电材料（209）装入孔中并固化。多个布线基板（206和210）具有通过固化的导电材料（209）电连接的布线层（211'）。位于固化的导电材料（209）外侧的布线层（211'）突出到周围区域的外侧。版权所有（C）2005，JPO＆NCIPI

64. 发明专利

JP2003318322A Interposer substrate, its manufacturing method, semiconductor device and its manufacturing method 审中-公开
标题翻译：插入式基板，其制造方法，半导体器件及其制造方法
公开(公告)号：JP2003318322A
公开(公告)日：2003-11-07
申请号：JP2002124415
申请日：2002-04-25
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAMURA SADASHI , TOMITA YOSHIHIRO , HIGASHIYA HIDEKI
IPC分类号： H01L23/12
CPC分类号： H01L2224/73204 , H01L2224/83192
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having high mounting reliability. SOLUTION: The semiconductor device (100) comprises: two or more wiring substrates (1, 2) having thermal expansion coefficients and areas different from each other and laminated so that the areas are sequentially reduced toward a side near a semiconductor bare chip (5) via a stress relaxing layer (3) disposed between the substrate (1) and the substrate (2) to form a circuit on an interposer substrate (41); one or a plurality of semiconductor bare chips (5) face-down mounted on the substrate (41) to relax a stress concentration at each mounting part when mounted on a mother board. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供具有高安装可靠性的半导体器件。解决方案：半导体器件（100）包括：两个或更多个布线基板（1,2），其具有彼此不同的热膨胀系数和面积，使得这些区域朝向靠近半导体裸芯片的一侧依次减小（5）经由设置在所述基板（1）和所述基板（2）之间的应力缓和层（3），以在中介基板（41）上形成电路; 一个或多个半导体裸芯片（5）面向下安装在基板（41）上，以在安装在母板上时放松每个安装部件处的应力集中。版权所有（C）2004，JPO

65. 发明专利

JP2003068778A Bump transfer base material, method for forming conductive bump, method for manufacturing bump transfer base material, method for manufacturing bump- shaped transfer base material, wiring substrate, and mounting body of semiconductor 审中-公开
标题翻译：阻尼传递基材，形成导电BUMP的方法，制造阻挡层基材的方法，制造形状转移基体材料的方法，接线基板和半导体的安装体
公开(公告)号：JP2003068778A
公开(公告)日：2003-03-07
申请号：JP2001257579
申请日：2001-08-28
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIGASHIYA HIDEKI , ANDO DAIZO , NAKAMURA SADASHI
IPC分类号： H05K3/34 , H01L21/60 , H05K3/20
CPC分类号： H01L2224/16225 , H01L2224/45144 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing minute conductive bumps with high accuracy and high productivity, and at a low cost. SOLUTION: While a bump transfer base material 104, comprising a wiring 101, conductive bumps 102 formed on the wiring 101, and a holding layer 103 for holding the conductive bumps 102, is bonded to a bump forming member 105, the holding layer 103 is removed, and the wiring 101 and the conductive bumps 102 are exposed on the surface of the bump forming member 105 to form the conductive bumps.
摘要翻译：要解决的问题：提供一种以高精度和高生产率并且以低成本制造微小导电凸块的方法。解决方案：包括布线101的凸块转移基材104，形成在布线101上的导电凸块102和用于保持导电凸块102的保持层103接合到凸块形成部件105，保持层103是并且布线101和导电凸块102暴露在凸块形成构件105的表面上以形成导电凸块。

66. 发明专利

JP2003017529A Method for manufacturing semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2003017529A
公开(公告)日：2003-01-17
申请号：JP2002124475
申请日：2002-04-25
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIGASHIYA HIDEKI , ANDO DAIZO , NAKAMURA SADASHI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16225 , H01L2224/29011 , H01L2224/29076 , H01L2224/32225 , H01L2224/45144 , H01L2224/73204 , H01L2224/83192 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To electrically connect a semiconductor element and a circuit board, which have electrodes arranged with a narrow pitch, to each other by using a conductive paste with a high reliability. SOLUTION: A semiconductor device, where a semiconductor part is electrically connected to the circuit board, and a method for manufacturing such a semiconductor device are provided. The manufacturing method comprises a step of forming a plurality of semiconductor electrodes in the semiconductor part, a step of forming a plurality of substrate electrodes in the circuit board, a first bonding step of bonding one of the semiconductor part and the circuit board to an intermediate connection body consisting of an insulating material, a step of forming a plurality of through-holes at the intermediate connection body according to the position of a plurality of semiconductor electrodes and the position of a plurality of substrate electrodes, a step of electrically connecting each substrate electrode to each semiconductor electrode via each through-hole, and a second bonding step of bonding the other of the semiconductor part and the circuit board to the intermediate connection body. Thus, the semiconductor device is provided.
摘要翻译：要解决的问题：通过使用具有高可靠性的导电膏将具有窄间距布置的电极的半导体元件和电路板电连接。解决方案：提供一种半导体器件，其中半导体部件电连接到电路板，以及制造这种半导体器件的方法。该制造方法包括在半导体部件中形成多个半导体电极的步骤，在电路板中形成多个基板电极的步骤，将半导体部件和电路基板之一接合到中间体的第一接合工序连接体，其由绝缘材料构成，根据多个半导体电极的位置和多个基板电极的位置在中间连接体处形成多个通孔的步骤，将每个基板电连接的步骤电极通过每个通孔连接到每个半导体电极，以及第二接合步骤，将半导体部件和电路板中的另一个接合到中间连接体。因此，提供了半导体器件。

67. 发明专利

JP2002368414A Method and apparatus for manufacturing highly conductive wiring board, and wiring board 审中-公开
标题翻译：制造高导线和导线板的方法和装置
公开(公告)号：JP2002368414A
公开(公告)日：2002-12-20
申请号：JP2001175456
申请日：2001-06-11
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAYA YASUHIRO , HIGASHIYA HIDEKI , KOYAMA MASAYOSHI , NAKAMURA SADASHI
IPC分类号： H05K3/40 , H05K1/11 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a wiring board which has remarkably high connection reliability even when high density wiring is formed in a limited area and to provide the manufacturing method and manufacturing apparatus of the wiring board. SOLUTION: The method for manufacturing a highly conductive wiring board is provided with a process for making a blind via hole where a base material holding material is set to be a base in an insulating base material where the base material holding member is arranged in a base, a process for filling the blind via hole with conductive particles and paste including binder components, which are loaded on the surface of the insulating base material by using a squeegee, and a process for arranging an absorbing sheet on the surface of the insulating base material and making the absorbing sheet absorb a part of the binder component of paste so as to increase the content of the conductive particles in paste.
摘要翻译：要解决的问题：即使在有限的区域中形成高密度布线并且提供布线板的制造方法和制造装置，也提供了具有非常高的连接可靠性的布线板。解决方案：制造高导电布线板的方法具有一种制造盲基通孔的方法，其中基材保持材料被设置为基体的绝缘基材中，其中基材保持部件布置在基部，通过使用刮板将负载在绝缘基材的表面上的导电性粒子和包含粘合剂成分的糊状物填充到盲孔的工序，以及在绝缘基材的表面上配置吸收片的工序并且使吸收片材吸收糊料的粘合剂成分的一部分，以增加糊料中的导电颗粒的含量。

68. 发明专利

JP2001345555A METHOD OF MANUFACTURING MULTILAYERED WIRING BOARD 失效
公开(公告)号：JP2001345555A
公开(公告)日：2001-12-14
申请号：JP2000162170
申请日：2000-05-31
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SUGAWA TOSHIO , ANDO DAIZO , NAKAMURA SADASHI , HIGASHIYA HIDEKI
IPC分类号： H05K3/40 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To properly perform the electric connection between the wiring layers on both sides of a substrate by enabling conductive paste to be filled in high density without voids and with high compressibility, in a blind via hole with its one side closed in an insulating base material. SOLUTION: This method includes processes for making a wiring layer 102 at one side of insulating base material 10, for forming film 103 for peeling on the opposite side of this base material, for forming a blind via hole 104 of the depth reaching the above wiring layer from the side of the opposite face of the insulating base material inclusive of this film for peeling, for squeezing conductive paste 105 from the surface of the film for peeling so as to charge the blind via hole with conductive paste, for degasing make the air pressure around the conductive paste vacuum low-pressure to degas the air or gas within the conductive paste out of the conductive paste, for peeling off the film for peeling, and for overlay this metal film as other wiring layer by compressing with a metal film 111 the conductive paste projecting from the surface of the insulating base material by the peeling of the film for peeling.

69. 发明专利

JP2001345539A METHOD OF MANUFACTURING EMBEDDED TYPE WIRING BOARD 失效
公开(公告)号：JP2001345539A
公开(公告)日：2001-12-14
申请号：JP2000164226
申请日：2000-06-01
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NAKAMURA SADASHI , ANDO DAIZO , SUGAWA TOSHIO , HIGASHIYA HIDEKI
IPC分类号： H05K3/40 , H05K3/22 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To increase the manufacturing yield of a wiring board by accurately aligning via holes and an embedded wiring pattern with each other. SOLUTION: This method of manufacturing an embedded type wiring board comprises a process of provisionarily bonding a first wiring material 4a on one face of an insulating base material 10; a process of bonding a release film 3 on the other face of the insulating base material; a process of forming the via holes 5 from one side of the insulating base material; a process of filling the via holes with the conductive paste 6; a process of separating the release film; a process of provisionarily bonding a second wiring material 4b on the exposed face of the insulating base material, which is exposed after the separation of the release film; a process of forming a wiring pattern 7 from the second wiring material at such places as to correspond to the via holes; and a process of applying heat and pressure to the wiring pattern, insulating material, and a conductive paste for embedding the wiring pattern in the surface of the insulating base material.

70. 发明专利

JP2001345528A WIRING BOARD AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001345528A
公开(公告)日：2001-12-14
申请号：JP2000166357
申请日：2000-06-02
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIGASHIYA HIDEKI , NAKAMURA SADASHI , ANDO DAIZO , SUGAWA TOSHIO
IPC分类号： H05K1/11 , H05K3/40
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board where stable via connection having little irregularities in connection resistance value is realized by improving the filling property of conductive paste, when a via hole whose bottom is closed is filled with the conductive paste, and to provide the method of manufacturing the printed wiring board. SOLUTION: Conductive particle density in the conductive paste 306, with which the via hole 304 is filled, has gradient in such a manner that one hole bottom side is made high density in the thickness direction of an electrical insulating base substance 302. This manufacturing method includes a process, where the via hole is formed so that wiring material is exposed to a hole bottom, to the electrical insulating base substance in which wiring material 301 is formed at least on a single side, a process where the via hole is filled with the conductive paste, a process where the electric insulating base substance and the conductive paste are heated and pressed, and a process for forming wiring which is electrically connected with the conductive paste. In the paste- filling process, filling is performed, while resin component and conductive particles in the conductive paste are being separated from each other.

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