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61. 发明专利

JPS63148350A CONTROL SYSTEM FOR VIRTUAL STORAGE OF SEGMENT BUFFER MEMORY 失效
公开(公告)号：JPS63148350A
公开(公告)日：1988-06-21
申请号：JP29602586
申请日：1986-12-12
申请人： HITACHI LTD
发明人： NISHIDA TAKEHIKO
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12
摘要： PURPOSE:To put the whole of a graphic data base on a segment buffer, by making the capacity of a segment buffer memory look like larger than a mounted physical memory capacity. CONSTITUTION:A central arithmetic processing part 1 and a graphic drawing data processing part 3 are equipped with large logical address areas capable of storing the whole of the graphic data base, and when reference or write to the area is generated, an address is converted from a logical address to the physical address of a mounted segment buffer memory 2 by an address conversion mechanism 5. At this time, when no physical address exists, the content of the address with low priority is returned from the memory 2 to an auxiliary storage device 4 by a virtual storage control mechanism 6, and the content of an absent address is read out and written from the device 4 on the vacant area of the memory 2. Afterwards, interrupted reference or write operation is restarted.

62. 发明专利

JPS6389963A PARALLEL INITIAL PROCESSING SYSTEM IN MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPS6389963A
公开(公告)日：1988-04-20
申请号：JP23461886
申请日：1986-10-03
申请人： HITACHI LTD
发明人： YUNO KAZUHARU , NISHIDA TAKEHIKO
IPC分类号： G06F15/177 , G06F9/445 , G06F15/16
摘要： PURPOSE:To shorten the rise time of a system as a whole, by performing an initial processing at the time of rising the system in parallel by an individual processor as possible, in a processing device having two or more processors. CONSTITUTION:An initial processing program in a ROM incorporated in a CPU13 is changed to shorten the time of the initial processing at the time of rising the system. Before the CPU13 executes the initial processing of a main memory 14, the initial processing program for a graphic subsystem existing on a fixed disk device 16 is transferred to and loaded on a graphic processor 11, and after that, the CPU13 starts up the graphic processor 11, and performs the initial processing of the main memory 14. The processor 11 reports the completion of the initial processing of the graphic subsystem to the CPU13 by applying interruption. Or, a method that the CPU13 refers a completion report register, and detects the completion of the processing of the processor 11, etc., can be adopted.

63. 发明专利

JPS62203441A ABNORMALITY PROCESSING CIRCUIT FOR REPEATER 失效
公开(公告)号：JPS62203441A
公开(公告)日：1987-09-08
申请号：JP4569186
申请日：1986-03-03
申请人： MITSUBISHI CABLE IND LTD , HITACHI LTD
发明人： HORI MASAHIKO , YOSHINO SUSUMU , SHIGENAGA KIYOSHI , YUNO KAZUHARU , NISHIDA TAKEHIKO , NAMATAME TADAO
IPC分类号： H04B3/36 , H04L12/28 , H04L12/40
摘要： PURPOSE:To ensure the communication in a normal segment by adopting the constitution that the state of a main control section is restored forcibly into the idle state by a reset signal outputted from a reset generating section when a signal exceeding a maximum packet length is inputted from any segment. CONSTITUTION:When the inputted signal exceeds the maximum packetlength and a state signal from a main control section 18 is consecutive for a prescribed time or more, the state detection of a state detection section 19 continues for a long time and a timer section 20 outputs a timeup signal. The main control section 18 to which a reset signal generated by a reset generation section 21 is supplied is restored to the idle state Id to interrupt the relay of both segments 2, 3. If one of the station of one segment 2(3) is faulty, the segment 2(3) of the faulty station is separated from other segment 3(2). Thus, no effect of the faulty station is given to the other segment 3(2), and the communication is ensured.

64. 发明专利

JPS62203195A CHARACTER FONT MEMORY CONTROLLER 失效
公开(公告)号：JPS62203195A
公开(公告)日：1987-09-07
申请号：JP4397886
申请日：1986-03-03
申请人： HITACHI LTD
发明人： NISHIDA TAKEHIKO , FUNIYU YUKIO
IPC分类号： G09G5/24 , B41J2/485 , G06F12/02 , G09G1/14

65. 发明专利

JPS6086629A BACKUP METHOD OF PROCESSING DEVICE 失效
公开(公告)号：JPS6086629A
公开(公告)日：1985-05-16
申请号：JP19414083
申请日：1983-10-19
申请人： HITACHI LTD
发明人： KOSAKAI NOBUO , KATOU TAKESHI , NISHIDA TAKEHIKO
IPC分类号： G06F11/20
摘要： PURPOSE:To back up all processing device of a system by providing network- side switching mechanisms and processing device-side switching mechanisms and switching and connecting adjacent processing devices successively in accordance with an abnormality signal. CONSTITUTION:If a data processing device 21 is faulty in a distributed data processing system, the device 21 transmits the abnormality signal to a processing device-side switching mechanism 42 adjacent to a network-side switching mechanism 51 through an abnormality signal line 31. Then, switching to a backup line 81 is operated, and a network 61 of the faulty data processing system is connected to a device 22, and processing operations of the system are executed by the device 22. Individual data processing systems perform this operation successively to connect a data processing device 24 for backup to a network 63 through a processing device-side switching mechanism 44, a network-side switching mechanism 53, etc. Thus, the device 24 continues processings instead of data processing devices 21-23 to back up all processing devices of the system.

66. 发明专利

JPS5934050B2 JPS5934050B2 - 失效
公开(公告)号：JPS5934050B2
公开(公告)日：1984-08-20
申请号：JP13351377
申请日：1977-11-09
申请人： Hitachi Ltd
发明人： NISHIDA TAKEHIKO , OONUMA KUNIHIKO
IPC分类号： H02J9/06 , H02J3/04

67. 发明专利

JPS5917468B2 JPS5917468B2 - 失效
公开(公告)号：JPS5917468B2
公开(公告)日：1984-04-21
申请号：JP10052776
申请日：1976-08-25
申请人： Hitachi Ltd
发明人： NISHIDA TAKEHIKO , OONUMA KUNIHIKO
IPC分类号： G06F11/28 , G06F7/00

68. 发明专利

JPS58166470A INFORMATION RECOVERY DEVICE OF IC STORAGE DEVICE 失效
公开(公告)号：JPS58166470A
公开(公告)日：1983-10-01
申请号：JP4891782
申请日：1982-03-29
申请人： HITACHI LTD
发明人： KOSAKAI NOBUO , NISHIDA TAKEHIKO
IPC分类号： G06F12/16 , G06F1/30 , G06F3/06 , G06F9/445 , G06F13/00
摘要： PURPOSE:To prolong the life of a floppy disk drive and to save a disuse electric power, by instruction from a microprogram during the starting of an arithmetic controller after power recovery. CONSTITUTION:An output sent out through a common bus 3 is applied to an inversion driver 13, whose output is supplied to the base of a transistor (TR) 14. Consequently, the TR 14 turns on and the power source switch 16 of a floppy disk drive (FD) 11 turned on by a relay coil 15 connected as a load to the collector. After confirming that the FD11 gets stable, the microprogram starts data transfer from the FD11 to an IC storage device 2. When the data transfer is not completed normally, the data transfer is retried as many times as specified. When the data transfer is completed normally, an off signal is sent to a disc power source FF12 immediately. Consequently, the TR14 is turned off to turns off the power source 17 of the FD11.

69. 发明专利

JPS5763585A Printing display control circuit 失效
标题翻译：打印显示控制电路
公开(公告)号：JPS5763585A
公开(公告)日：1982-04-17
申请号：JP13772880
申请日：1980-10-03
申请人： Hitachi Ltd
发明人： NISHIDA TAKEHIKO
IPC分类号： G06F3/12 , B41J5/44 , G06F3/14 , G06F3/153 , G06K15/12 , G09G1/06 , G09G5/24

70. 发明专利

JPS5518706A PARALLEL ADDER CIRCUIT 失效
公开(公告)号：JPS5518706A
公开(公告)日：1980-02-09
申请号：JP8947378
申请日：1978-07-24
申请人： HITACHI LTD
发明人： NISHIDA TAKEHIKO , MAEJIMA HIDEO
IPC分类号： G06F7/50 , G06F7/507
摘要： PURPOSE:To reduce greatly the total number of elements without changing an adding speed by using signal transfer elements, whose switching operation are controlled by outputs of half adders for respective digits, as carry transfer elements and then by connecting all of them in series. CONSTITUTION:For respective digits, logical gates 1a to 1d and half adders 2a to 2d are provided, and signal transfer elements 11a to 11d controlled by the half adders are connected in series. Further, carry-signal generating tansistors 12a to 12d and 15a to 15d are connected between respective signal transfer elements for corresponding digits and post-stage signal transfer elements. In addition, signal transfer circuit 16 which operates where there is no carry signal from the prior digit of the lowest digit and circuit 17 which operates when there is the signal are provided. The output of an addition result is outputted from OR-ELSE gate 19d to 19a in the former case and from gate 20a to 20d in the latter case. Therefore, the adding speed will not be reduced.

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