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61. 发明专利

JPS62146041A TIME DIVISION MULTIPLEX COMMUNICATION SYSTEM 失效
公开(公告)号：JPS62146041A
公开(公告)日：1987-06-30
申请号：JP28819185
申请日：1985-12-20
申请人： HITACHI LTD
发明人： TAKAHASHI YASUHIRO , HIYAMA KUNIO
IPC分类号： H04Q11/04 , H04J3/16 , H04J3/22 , H04L12/43
摘要： PURPOSE:To enhance the storage capability of low-speed data lines in the time division multiplexing system where high-speed and low-speed data exist together, by generating a group frame with a main frame and a slave frame different in time slot synchronizing code value from the main frame and transmitting and receiving the data of a terminal equipment at each designated time slot in the group frame. CONSTITUTION:The number of time slots at the intervals of which frames should be transmitted and received is set to a frame mode register 18 in accordance with relations between the transmission capacity of one time slot in a subframe on a loop transmission line 1 and the line speed of a connected terminal equipment, and one representative subframe to be transmitted and received is set to a frame number register 19, and a frame number to be transmitted and received is determined based on both set values by a frame number determining logic circuit 17. If the coincidence signal between this number and the value indicated by a subframe counter 15 and that between the value indicated by a time slot counter 16 and the output value of a transmission/reception time slot number register 20 coincide with each other in an AND circuit 23, a transmission gate 24 and a reception gate 25 are opened. Data of the terminal equipment is transmitted and received at a designated time slot in a designated frame.

62. 发明专利

JPS60167593A SIGNAL REPEATING SYSTEM 失效
公开(公告)号：JPS60167593A
公开(公告)日：1985-08-30
申请号：JP2168484
申请日：1984-02-10
申请人： HITACHI LTD
发明人： HOSHI TOORU , HIYAMA KUNIO
IPC分类号： H04Q11/04
摘要： PURPOSE:To enable transmission of circuit conditions efficiently by transmitting repetitively a channel consisting of a bit for transmitting sound information and that for transmitting data at every certain period and by utilizing a communication device to transmit and receive channel information between terminals. CONSTITUTION:The state of a circuit which an SLIC3 monitors is stored in a bit position S of a buffer 6 and accumulated in a buffer of an interface 7 in the same manner as a sound. When the channel number of a loop tranmission line becomes a preset one, the interface 7 transmits state signals of a sound and circuit to a loop transmission line. On the other hand, the state signal is accumulated in a buffer of an interface 10 by the channel number in terms of node 200, and transfered to a buffer 12 of a trunk 15. Here, sound bits are transmitted to a cordic 13, in which they are converted into an analog signal and transmitted to a telephone exchange.

63. 发明专利

JPS6042962A DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPS6042962A
公开(公告)日：1985-03-07
申请号：JP15014083
申请日：1983-08-19
申请人： HITACHI LTD
发明人： HOSHI TOORU , SUZUKI MICHIO , TAKENOUCHI HIROO , KONASE TOSHIAKI , HIYAMA KUNIO
IPC分类号： H04L29/06 , H04L12/00
摘要： PURPOSE:To obtain a data communication system attaining connection of an opposite party with the dial operation from a terminal device by providing a connecting means converter provided with a register having a serial/parallel converting function for transmitting and receiving data signal, a register for transmitting and receiving a control signal and a means controlling them between data terminal devices and a network. CONSTITUTION:A signal RS is set with a call request (state 1) from a start-stop data terminal device DTE1, the signal is written in a reception register R0 of a register 15, and the signal is read by an MPU16. The MPU16 writes ''1'' to a transmission shift register 13 so as to transmit continuously ''1'' from the said shift register 13. When a ''1'' signal on a line R is received from the network in response to it (state 2), it is received by a reception shift register 14 and it is read by the MPU16. The MPU16 conducts code conversion and parity bit conversion as required and writes a reception signal to the transmission shift register 13. Thus, numeric information is transmitted on a line T according to a clock from a clock circuit 17 via the said shift register 13.

64. 发明专利

JPS59228445A DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JPS59228445A
公开(公告)日：1984-12-21
申请号：JP10259483
申请日：1983-06-10
申请人： HITACHI LTD
发明人： SUZUKI MICHIO , HOSHI TOORU , TAKENOUCHI HIROO , KONASE TOSHIAKI , HIYAMA KUNIO
IPC分类号： H04L29/10 , H04L12/00 , H04L11/02
摘要： PURPOSE:To reduce the number of signal lines between the network side and the terminal side by providing separately an interface converting device to the network side and the terminal side in connecting a data exchange network to data terminal devices in accordance with the protocol of the CCITT recommendations 21. CONSTITUTION:In connecting a data terminal device DTE having an X21 interface and a line terminator DCE of the data exchange network, interface converting devices CONV1, 2 are provided between both devices. The converting device CONV1 multiplexes the information on lines T and C from the terminal device DTE of the X21 interface, converts the result to manchester codes and the result is transmitted further to a line L while its transmitting speed is increased. On the other hand, the information from the device DCE is converted to Manchester decoding and demultiplexed into the information of the lines R and I and the result is transmitted to the terminal device DTE. The CONV2 of the device DCE conducts the similar operation. Thus, the number of signal lines between the terminal device DTE and the device DCE is decreased from 5 lines (used in a conventional system) into 1 line.

65. 发明专利

JPS59117344A Failure preventing device in data communication system 失效
标题翻译：数据通信系统中的故障预防设备
公开(公告)号：JPS59117344A
公开(公告)日：1984-07-06
申请号：JP22612582
申请日：1982-12-24
申请人： Hitachi Ltd
发明人： KAWAKITA KENJI , HIYAMA KUNIO , TAKAHASHI YASUHIRO
IPC分类号： H04J3/14 , H04J3/06
CPC分类号： H04J3/06
摘要： PURPOSE:To prevent a failure by detecting the failure of a counter by a reset signal and a timing signal of the counter. CONSTITUTION:When the timing signal Ti changes twice or more in one frame, an output of a flip-flop 401 rises once or more and a flip-flop 402 is set. Further, when a reset signal TFRM is turned on and a signal Ti is turned on, an AND gate 403 is set. In this case, a flip-flop 406 is reset, the signal Ti is inhibited by an AND gate 407 to prevent a failure.
摘要翻译：目的：通过复位信号和计数器的定时信号检测计数器的故障来防止故障。构成：当定时信号Ti在一帧中改变两次或更多时，触发器401的输出上升一次或更多并且触发器402被置位。此外，当复位信号TFRM导通并且信号Ti导通时，设置与门403。在这种情况下，触发器406被复位，信号Ti被与门407阻止以防止故障。

66. 发明专利

JPS59117340A Device for preventing influence of failure 失效
标题翻译：防止故障影响的设备
公开(公告)号：JPS59117340A
公开(公告)日：1984-07-06
申请号：JP22612682
申请日：1982-12-24
申请人： Hitachi Ltd
发明人： TAKAHASHI YASUHIRO , HIYAMA KUNIO , KAWAKITA KENJI
IPC分类号： H04B13/00 , H04J3/14
CPC分类号： H04J3/14
摘要： PURPOSE:To prevent the influence of a failure at out of synchronism by inhibiting immediately the transmission and receiving after out of synchronism is detected. CONSTITUTION:The content of a channel counter is received by a decoder 301 and whether or not out of synchronism occurs is discriminated by making a timing signal delayed by one channel by an FF304 coincident with the synchronism pattern of the content of a channel arrived at that point of time. Further, when out of synchronism is detected, the FF303 is reset, a gate 306 is closed so as to inhibit the permission of operation of transmission and receiving circuit to a terminal device side. Further, when a frame effective region is indicated, the gate 306 is opened, and the permission of operation of the transmission and receiving circuit is transmitted to the terminal device side.
摘要翻译：目的：通过在同步之后立即禁止异步发现和接收，防止失效对同步的影响。构成：信道计数器的内容由解码器301接收，并且通过使FF304与通过到达该信道的信道的内容的同步模式相一致来确定延迟一个信道的定时信号来判别是否发生同步时间点此外，当检测到不同步时，FF303被复位，门306被关闭，从而禁止对终端设备侧的发送和接收电路的操作的允许。此外，当指示帧有效区域时，门306打开，并且发送和接收电路的操作允许被发送到终端设备侧。

67. 发明专利

JPS58204695A Data communicating system 失效
标题翻译：数据通信系统
公开(公告)号：JPS58204695A
公开(公告)日：1983-11-29
申请号：JP8663682
申请日：1982-05-24
申请人： Hitachi Ltd
发明人： HIYAMA KUNIO , KAWAKITA KENJI , TAKADA OSAMU
IPC分类号： H04Q11/04 , H04M11/06
CPC分类号： H04M11/068
摘要： PURPOSE:To transmit/receive voice information and data information at a communicating node device with a channel at the same time and to connect lots of terminals to a common transmitting line, by producing the channel including bit for voice information transmission and bit for data transmission repetitively at a prescribed period. CONSTITUTION:Plural communicating nodes are connected to a loop transmission line 1200, and the transmission/reception is controlled with a transmission control section 400 of the node devices. The synchronizing area of a receiving signal is discriminated at a frame synchronizing section 100, a channel number in the frame is discriminated at a channel control section 200 to instruct the line exchange area of the frame and the operating control of the nodes and the like. Further, a terminal control section 500 performs the control of transmission/ reception with a corresponding terminal device 100 and the transmission control of transmission/reception with the control section 400, and the connection and initialyzing processing and the like are done with the program of a processor 300. Further, the node devices transmit/receive the voice signal and the data information at the same time and connect lots of the terminal devices 1000 to the transmission line 1200.
摘要翻译：目的：通过在同一通道的通信节点设备上发送/接收语音信息和数据信息，并将大量终端连接到公共传输线，通过产生包括用于语音信息传输的位和用于数据传输的位的信道在规定期间重复。构成：多个通信节点连接到环路传输线路1200，并且通过节点设备的传输控制部分400来控制发送/接收。接收信号的同步区域在帧同步部分100处被鉴别，在信道控制部分200鉴别帧中的信道号，以指示帧的线路交换区域和节点的操作控制等。此外，终端控制部500执行与对应的终端装置100的发送/接收的控制以及与控制部400的发送/接收的发送控制，并且连接和初始化处理等通过处理器300.此外，节点装置同时发送/接收语音信号和数据信息，并将许多终端装置1000连接到传输线路1200。

68. 发明专利

JPS5821943A DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPS5821943A
公开(公告)日：1983-02-09
申请号：JP11906781
申请日：1981-07-31
申请人： HITACHI LTD
发明人： HIYAMA KUNIO , KAWAKITA KENJI , TAKADA OSAMU
IPC分类号： H04L12/42 , H04L12/43 , H04L12/437
摘要： PURPOSE:To detect a faulty state, by detecting through at least one node device that the idle/busy display bits of an optional continuous channel are all displayed in the busy state. CONSTITUTION:A frame formation control part 900 stores the frame information that has passed round a loop in a memory 1 within the part 900 by an amount equivalent to a frame via a transmitting/receiving part 400A of a transfer control part. At the same time, the part 900 produces the clock for transmission and produces a pattern of a synchronizing region at first based on said clock. After that, the memory is read to form a frame. Furthermore the part 900 has a function to monitor a fault and then displays forcibly the idle/busy display bit of each channel in an idle state when the state, under which all idle/busy display bits of each channel display the busy state, is continuous more than a certain frequency is detected for both the circuit exchange region and the packet exchange region.

69. 发明专利

JPS5821940A DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPS5821940A
公开(公告)日：1983-02-09
申请号：JP11906481
申请日：1981-07-31
申请人： HITACHI LTD
发明人： HIYAMA KUNIO , KAWAKITA KENJI , TAKADA OSAMU
IPC分类号： G06F13/00 , H04L5/22 , H04L12/43
摘要： PURPOSE:To eliminate the limitation for the processing speed at the terminal device side, by displaying invalidity for the validity display bit of a channel in case the data to be sent in a certain period is not in time when the communication of data is carried out between the communication nodes which are connected to a common signal transmission line. CONSTITUTION:A transmission request signal SREQ is turned on at a terminal device when the transmitting data is completed, and then the transmitting data SD and a transmission request FF516 are set to a transmitting buffer 515. Then the output signal of the FF516 is fed to a transfer controlling part in the form of a validity display bit and along with the data information. When the coincidence of the channel numbers is detected before the transmitting data given from the terminal device is complete, the validity display bit of the data SD becomes zero since the FF516 is reset before the data is transmitted. This shows that the transmitting data is invalid. Accordingly the processing speed is low at the side of the terminal device, and the invalidity is displayed in case the transmitting data is not complete. Thus the terminal device can transmit the data at an optional speed which is lower than a certain period.

70. 发明专利

JPS56118127A DATA TRANSMISSION SYSTEM AND BUS COUPLER 失效
公开(公告)号：JPS56118127A
公开(公告)日：1981-09-17
申请号：JP2050280
申请日：1980-02-22
申请人： HITACHI LTD
发明人： URUGA HIDEO , TAKENOUCHI HIROO , HATADA MINORU , HIYAMA KUNIO
IPC分类号： G06F13/36 , G06F9/52 , G06F13/40 , G06F15/16 , G06F15/173 , G06F15/177
摘要： PURPOSE:To simplify the constitution of the entire system, by making the upper- rank and lower-rank bus couplers with the same circuit constitution. CONSTITUTION:Gates G1, G2, G4 control the transmission signal input to terminals S1, A1, D1 to be output at terminals S2, A2, D2, and the switching of the gates is controlled with the output of a competition control circuit ARB. Gates G3, G5 control the signal for reception inputted to the terminals A2, D2 to be output at the terminals A1, D1, and the on/off of the gates is controlled with the output of comparators CMPL, CMPH. CMPL compares the content of an address setter ASETL with the signal at the terminal A2, and CMPH compares the content of the address setter ASETH with the signal at the terminal A2.

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