专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明专利

JPS61221886A BINARY CODING SYSTEM FOR PICTURE IDENTIFICATION 失效
公开(公告)号：JPS61221886A
公开(公告)日：1986-10-02
申请号：JP6450885
申请日：1985-03-27
申请人： FUJITSU LTD
发明人： YOSHIDA SHIGERU
IPC分类号： G06T5/00 , G06K9/36 , G06K9/38 , G06T7/00
摘要： PURPOSE:To identify a character/line drawing or a variable density drawing at a high speed through a simple circuit, by obtaining the multi-value coded data obtained from at least two pieces of unit threshold value of different levels for each picture element and estimating the slope of the picture density of a block. CONSTITUTION:A means A is provided to turn the multi-gradation data on each picture element of a picture containing a character/line drawing and a variable density drawing into a duther form together with a multi-value coding means B which compares the multi-gradation data with two pieces of unit threshold value to obtain the multi-value coded data, a identifying means C and a selection output means D. The combination of the multi-value coded data of each picture element forming a block is corresponding to the slope of density within the block. A table where te combinations of the multi- value coded data corresponding to the gentle and steep slopes are set opposite to the variable density and character/line drawings respectively is prepared. Then the multi-value coded data on each block is compared with said table for identification whether the relevant block is equal to the character/line drawing or the variable density drawing. Based on the result of this identification, the unit threshold value picture or the dither threshold value picture can be used selectively for each block.

62. 发明专利

JPS61221885A PICTURE IDENTIFYING SYSTEM 失效
公开(公告)号：JPS61221885A
公开(公告)日：1986-10-02
申请号：JP6450985
申请日：1985-03-27
申请人： FUJITSU LTD
发明人： YOSHIDA SHIGERU
IPC分类号： G06K9/20 , G06K9/36 , G06T7/00
摘要： PURPOSE:To reduce greately the degree of erroneous identification of pictures by obtaining a degenerated state from the multi-value coded data of each picture element and identifying whether the noticed picture elements are equal to a character/line drawing or a variable density drawing based on the degenerated states of the noticed picture elements and their reference picture elements and with reference to a maximum likelihood deciding table. CONSTITUTION:The multi-value coded data is obtained for each picture element by means of plural pieces of unit threshold value. Based on these data, the degenerated state is obtained for each block consisting of plural picture elements. Then a picture of the noticed picture elements is identified with a high degree with reference to a maximum likelihood deciding table obtained from the probability with which the state of a noticed block is produced from the state of the block produced previously and based on the degenerated states of both noticed and reference picture elements. In other words, a detecting system using the unit threshold value is used to identify every block of plural picture elements whether a picture in an original is equal to a character/line drawing or a variable density drawing in case both character/line and variable density drawings are mixed in the original. Then the block is identified as a variable density drawing and therefore binary coded with the threshold value of a dither matrix. While the block is binary coded with the single threshold value when it is identified as a character/line drawing respectively.

63. 发明专利

JPS6174456A Block line memory control system 失效
标题翻译：块线记忆控制系统
公开(公告)号：JPS6174456A
公开(公告)日：1986-04-16
申请号：JP19584684
申请日：1984-09-20
申请人： Fujitsu Ltd
发明人： OKADA YOSHIYUKI , YOSHIDA SHIGERU , SATO TORU
IPC分类号： H04N1/415 , H04N1/41
摘要： PURPOSE: To utilize effectively a memory capacity by starting simultaneously read from plural line memories at the start point of time of picture data write of the final line and using less capacity of the plural line memories to the picture data.
CONSTITUTION: Latch signals a, b, c of registers 21, 25, 26, a switching signal (d) of a multiplexer 22 and write control and read control signals e, f of odd and even line memories 23, 24 are outputted respectively from a system control circuit 27. The signals e, f are transmitted according to a data request signal (g) by the end of compression processing of a block line from the data compression circuit of the next stage. A picture data A is latched to a register 21 of the system by using the signal (a) and the multiplexer 22 switching the memories 23, 24 constituting the block line according to the switching signal (d). Then the picture data is subjected to buffering by using the memories 23, 24 with less capacity and the memory capacity is utilized easily.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在最后一行的图像数据写入的开始时刻开始同时从多行存储器读取并且使用较少的多行存储器的容量来获得图像数据，从而有效地利用存储器容量。构成：寄存器21,25,26的锁存信号a，b，c分别由多路复用器22的切换信号（d）和奇数和偶数行存储器23,24的写控制和读控制信号e，f分别从系统控制电路27.信号e，f根据来自下一级的数据压缩电路的块行的压缩处理结束时的数据请求信号（g）被发送。图像数据A通过使用信号（a）锁存到系统的寄存器21，多路复用器22根据切换信号（d）切换构成块线的存储器23,24。然后，通过使用容量较小的存储器23,24对图像数据进行缓冲，容易使用存储容量。

64. 发明专利

JPS60182867A PAPER MEDIUM INFORMATION RECORDING SYNCHRONIZING SYSTEM 失效
公开(公告)号：JPS60182867A
公开(公告)日：1985-09-18
申请号：JP3913284
申请日：1984-02-29
申请人： FUJITSU LTD
发明人： YOSHIDA SHIGERU , OKADA YOSHIYUKI , SATOU TOORU
IPC分类号： H04N1/36
摘要： PURPOSE:To obtain a recording synchronism system possible for transmission/ reception independently of the difference in the resolution between the transmission side and reception side by reading an information bit detecting mark changed in the same size and in stripe as one bit of the transmission side picture information before start of scanning and transmitting the result. CONSTITUTION:When a picture data corresponding to a scanning line 3a is given to a CPU13 and a pattern having alternately black and white levels appears, the CUP13 recognizes that the scanning of the information bit detecting mark is started, the center position of the main scanning at each information bit is obtained and stored in a memory 14a. When a picture data corresponding to a scanning line 3b is given to the CPU13, the CPU13 recognizes the start of picture data and the picture data is stored sequentially in a memory 14b. Then the center position in the sub-scanning direction is obtained from the picture data stored in the memory 14b, the center point of each information bit is obtained from the center position in the main scanning direction stored in a memory 13 and logical ''1'' or ''0'' of each information bit is restored from the main scanning line passing through the center point.

65. 发明专利

JPS59117864A System for controlling data compression and expansion 失效
标题翻译：用于控制数据压缩和扩展的系统
公开(公告)号：JPS59117864A
公开(公告)日：1984-07-07
申请号：JP23469582
申请日：1982-12-24
申请人： Fujitsu Ltd
发明人： OKADA YOSHIYUKI , YOSHIDA SHIGERU , SATOU TOORU
IPC分类号： H04N1/417 , G06T9/00 , H04N1/41
CPC分类号： H04N1/41
摘要： PURPOSE:To discriminate easily compression and non-compression in the unit of one line by comparing amount of compressed data and non-compressed data to a picture data for one line share and adding selectively a tag bit for compression information depending on the result of comparison. CONSTITUTION:The picture data for one line share of input original is stored in a non-compression data buffer 2, a compressed data is formed by a data compression section 1 and the data is stored in a compression data buffer 3. This compressed data is compared with a constant L at a data amount comparing section 4. The comparison section 4 transmits the result of comparison to a code generating section 5 and a multiplexer MPX6. When it is decided that the compressed data is less by the constant L, the MPX6 transmits the compressed data of the buffer 3 in succession to a code EOL+*1*2 from the generating section 5 and when decided much, the non-compressed data of the buffer 2 is transmitted in succession to the code EOL+*1*2. The *1 is a tag bit representing the distinction of one-dimention and two-dimension and the *2 is a tag bit representing the distinction of compression and non-compression.
摘要翻译：目的：通过将压缩数据和非压缩数据的数量与一个线路共享的图像数据进行比较，以一行的方式区分容易的压缩和非压缩，并根据比较结果选择性地添加压缩信息的标签位。构成：将输入原稿的一行共享的图像数据存储在非压缩数据缓冲器2中，压缩数据由数据压缩部1形成，数据存储在压缩数据缓冲器3中。该压缩数据为与数据量比较部分4上的常数L相比较。比较部分4将比较结果发送到代码生成部分5和多路复用器MPX6。当确定压缩数据小于常数L时，MPX6将来自生成部5的代码EOL + * 1 * 2连续地发送缓冲器3的压缩数据，并且当大量确定时，非压缩数据缓冲器2的连续发送到代码EOL + * 1 * 2。 * 1是表示一维和二维的区别的标记位，* 2是表示压缩和非压缩的区别的标记位。

66. 发明专利

JPS58106959A DATA COMPRESSION CIRCUIT 失效
公开(公告)号：JPS58106959A
公开(公告)日：1983-06-25
申请号：JP20570881
申请日：1981-12-19
申请人： FUJITSU LTD
发明人： YOSHIDA SHIGERU , MATSUDA TADASHI
IPC分类号： H04N1/417 , H04N1/41
摘要： PURPOSE:To shorten the addition time to make the operation of a compression circuit high-speed, by providing a means, which accesses pictue data and a PROM simultaneously, and a means which compensates the lag of data processings of simultaneously accessed results. CONSTITUTION:A PROM controller 30' consists of a PROM 12 and a register 13', and a picture element signal due to an output 20 from a line memory 10 is inputted to the register 13' directly. At this time, an address counter 11 is counted up by a microcommand from the register 13', and the output 20 is applied from the memory 10 to the register 13' by the address designated by the counter 11. Simultaneously, the PROM 12 is accessed by a status address signal 22, and a status address signal 21 and a microcommand signal 23 are outputted to the register 13', and an RL counter 14 is accessed by the register 13', and its contents are processed. The register 13' is accessed directly to compensate the lag of the data processing time, thus shortening the addition time.

67. 发明专利

JPS579171A RESTORATION CIRCIT FOR COMPRESSED DATA 失效
公开(公告)号：JPS579171A
公开(公告)日：1982-01-18
申请号：JP8226980
申请日：1980-06-18
申请人： FUJITSU LTD
发明人： YOSHIDA SHIGERU , KONDOU ISAO , HORIE MASAKATSU
IPC分类号： H03M5/04 , H03M7/46 , H04N1/419
摘要： PURPOSE:To speed up the restoring process to about two times, by giving the shift function of 2 -bit and 1-bit to a shift register which is used to restore the picture data from the run length with equal length to the compressed data. CONSTITUTION:First, a run length is stored in an RL latch circuit 14 and a value of the content of the circuit 14 except the least significant bit LSB and the value of a counter 23-2 are compared at a comparison circuit 15. A 2-bit shift signal 32 is outputted until these values are coincided. This 2-bit signal gives signal to a shift register 21 while shifting two-bit according to black and white mode of an FF 10, and the number of shifts is counted with the counters 22-2 and 23-2. If the value in a shift number count circuit 22 reaches a value less by one than the number of bits in a register 21, a control pulse generating circuit 24 outputs a one bit shift signal 31. Further, the same processing as that for 2-bit is made with the signal 31.

68. 发明专利

JPS56154785A VIDEO SIGNAL GENERATING SYSTEM 失效
公开(公告)号：JPS56154785A
公开(公告)日：1981-11-30
申请号：JP5765080
申请日：1980-04-30
申请人： FUJITSU LTD
发明人： YOSHIDA SHIGERU , KIMURA MASATOSHI , KONDOU ISAO , HORIE MASAKATSU
IPC分类号： G06K15/10 , G06F3/153 , G06T11/00 , G06T11/20 , G09G1/06 , G09G5/00 , G09G5/14 , G09G5/36 , G09G5/377 , G09G5/40

69. 发明专利

JPS55136753A COMPRESSED DATA RECOVERY SYSTEM 失效
公开(公告)号：JPS55136753A
公开(公告)日：1980-10-24
申请号：JP4394979
申请日：1979-04-11
申请人： FUJITSU LTD
发明人： YOSHIDA SHIGERU , KOSEKI MINORU , AIKAWA KAZUHISA , HORIE MASAKATSU
IPC分类号： H03M5/04 , H04N1/41 , H04N1/417 , H04N1/419
摘要： PURPOSE:To change the decoding speed, by writing in this set value to the memory at a bundle, when the number of bits of signal to be decoded is more than a set value. CONSTITUTION:The run length code is inputted to the latch 10, and block and white information of video element train is inputted to FF12 for set or reset. The number of video elements of the run length code and the output of the setter 34 are compared at the comparison circuit 30, and if the number of elements of run length code is greater, the control pulse generation circuit 16 outputs the control signal S2 to perform batch write-in of the number of bits set with the setter 34 in the memory 24. The decoding information for the remaining number of bits is written in the register 22 bit by bit. When the addition of the remaining number of bits reaches the set number in the decoding of run after that, batch write-in is made to the memory 24.

70. 发明专利

JP2002297568A CODING APPARATUS FOR STRUCTURED DOCUMENT AND RECORDING MEDIUM 失效
公开(公告)号：JP2002297568A
公开(公告)日：2002-10-11
申请号：JP2001094920
申请日：2001-03-29
申请人： FUJITSU LTD
发明人： YAHAGI HIRONORI , YOSHIDA SHIGERU
IPC分类号： G06F17/21 , G06F12/00 , G06F17/30
摘要： PROBLEM TO BE SOLVED: To allow suppressing element contents and attribute names efficiently for achieving both of a reduction in operating memory amount and an improvement in processing speed in a coding apparatus for structured document. SOLUTION: In the apparatus to code the attribute names and/or character strings of the element contents with correlating the names and/or strings with applicable element names as a shorter character string of character codes for a structured document, a coding means (a means including a correspondence table creating means 106 and an conversion means 108) to create correspondence tables by applicable element name for the names and/or the strings, perform coding by using the tables summarize with collecting only the names concurrently with applying the coding and also perform coding of the names as the shorter character string is equipped.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式