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61. 发明专利

JPH04256241A SIGNAL TRANSMITTER 失效
公开(公告)号：JPH04256241A
公开(公告)日：1992-09-10
申请号：JP1732191
申请日：1991-02-08
申请人： FUJITSU LTD
发明人： MIURA NORIHISA , TAKEDA SATOSHI , TANIGUCHI MITSUKI , NAKADE HIROSHI
IPC分类号： H04L7/10 , H04L29/02 , H04Q3/545
摘要： PURPOSE:To prevent production of an error in a signal of an existing signal transmitter by providing a synchronization means taking a reset release signal output timing as a change point of a clock to an output of a power-on reset circuit. CONSTITUTION:A synchronization means 3-2 taking a reset release signal output timing as a clock change point is provided to an output of a power-on reset circuit 3-1. Thus, a point of time when a signal is sent from an output control section 2 to a 2nd signal line adjacent to a 1st signal line through which a signal of an existing signal transmitter is sent by applying power of an extended signal transmitter is a clock change point and coincident with a change point of data. Thus, since discrimination of 1,0 of the data is not implemented at this pint of time by decreasing the level resulting from coupling, no data error is caused.

62. 发明专利

JPH0366240A CLOCK CHANGEOVER CIRCUIT 失效
公开(公告)号：JPH0366240A
公开(公告)日：1991-03-20
申请号：JP20301289
申请日：1989-08-04
申请人： FUJITSU LTD
发明人： NAKADE HIROSHI , TAKEDA SATOSHI , YAMAZAKI HIROSHI , MIURA NORIHISA
IPC分类号： H04L1/22 , H04L7/00
摘要： PURPOSE:To prevent data slip at clock changeover by providing 2 stages of clock interrupt detection circuits and phase-locking an output of a system selected at present with an output of a system to be selected after that before the output of a current phase locked loop into the output of a standby phase locked loop. CONSTITUTION:When an active (N system) input clock is interrupted due to a fault of a transmission line or the like, a clock interrupt detection circuit 7 supplies a detection signal output to a SEL 8 and a CONT 13. The SEL 8 is switched from the clock input side of the N system into the output clock of the E system PLL 12. Moreover, the SEL 14 is switched from the input side of the PLL 9 (N system) into the input side from the PLL 12 (E system) and the output of the PLL 12 is outputted from the SEL 14. As a result, two stages of clock interrupt detection circuits are provided to phase-lock the output of the PLL 9 of the system (N system) selected at present into the output of the PLL 12 of the system (E system) going to be selected before the SEL 14 selects the output of the PLL 9 into the output of the PLL 12 thereby preventing the data slip at the clock switching in an opposite station.

63. 发明专利

JPH02166846A MULTIFRAME DETECTING CIRCUIT 失效
公开(公告)号：JPH02166846A
公开(公告)日：1990-06-27
申请号：JP32508688
申请日：1988-12-20
申请人： FUJITSU LTD
发明人： MIURA NORIHISA , TAKEDA SATOSHI , SUMITANI TAKAO , KANEKO HIROYUKI
IPC分类号： H04J3/06
摘要： PURPOSE:To accurately detect the abnormality of a transmission line by outputting no abnormality signal when the transmission line is normal and its own multiframe detection circuit is abnormal, and outputting the abnormality signal only when the transmission line is surely abnormal. CONSTITUTION:When its own multiframe detection circuit 1 is abnormal, the abnormality signal is outputted from the circuit 1, but because phase difference between the head bit of the multiframe of its own handling group HG and the head bit of the multiframe of another HG does not change since the transmission line is not abnormal, the abnormality signal is not outputted from a phase difference detection circuit 4, and a supervision circuit 5 does not consider it to be 'abnormality'. When the transmission line to receive its own HG becomes abnormal, since the position of the head bit of the multiframe which the circuit 1 is detecting does not shift, the abnormality signal is outputted from the circuit 1. Besides, since the position of the head bit of the multiframe of another HG which another multiframe detection circuit 2 is detecting shifts gradually, the abnormality is outputted from the circuit 4.

64. 发明专利

JPH0275237A ALARM TRANSFER SYSTEM BY BIT STEAL 失效
公开(公告)号：JPH0275237A
公开(公告)日：1990-03-14
申请号：JP22606288
申请日：1988-09-09
申请人： FUJITSU LTD
发明人： MATSUSHIMA HIROMASA , TAKEDA SATOSHI , NAKADE HIROSHI , MIURA NORIHISA , YAMAZAKI HIROSHI
IPC分类号： H04J3/14
摘要： PURPOSE:To simply transfer an alarm detected by a slave station to a monitor section without provision of a large sized transmission equipment by sending the alarm through a data transmission line. CONSTITUTION:A communication system consists of a master station 10, a transmission line 12, a slave station 14, a subscriber 16 and a monitor section 18, the subscriber 16 such as a telephone subscriber slave station 14 is provided with a multiplexer 14b, and the master station 10 is provided with a demultiplexer 10b and a voice data from the subscriber is sent through the transmission line with multiplexing. Then a bit number of each channel data of a prescribed frame is selected to be less than that of other frames by one bit, alarm information is sent from the slave station 14 to the master station 10 as the LSB of each channel data of a prescribed frame and the alarm information sent from the slave station 14 is transferred to the monitor section 18 by the master station 10. Thus, the alarm detected by the slave station is simply transferred to the monitor section without provision of a large sized transmission installation.

65. 发明专利

JPH0271632A ALARM HOLDING CIRCUIT 失效
公开(公告)号：JPH0271632A
公开(公告)日：1990-03-12
申请号：JP22393388
申请日：1988-09-07
申请人： FUJITSU LTD
发明人： YAMAZAKI HIROSHI , TAKEO HIROSHI , TAKEDA SATOSHI , NAKADE HIROSHI , MIURA NORIHISA
IPC分类号： G08B23/00 , H04B3/46 , H04B17/00 , H04M3/10
摘要： PURPOSE:To attain high reliability and a low cost by using an electronic relay with a long service life by providing an electronic relay for holding and an electronic relay for outputting at an alarm supervisory part. CONSTITUTION:When a fault occurs at a part corresponding to a switch SW1 in a device part 10, the switch SW1 is closed, thereby, the electronic relay 22 for holding and the electronic relay 24 for outputting are operated, and the relay 24 informs the occurrence of the fault at the part in the device part 10 corresponding to the switch SW1 to an alarm display part, and, for example, lights the lamp of the part. Also, the relay 22 completes a path to the ground and self-holds it, and also, controls the relay 24 so as to be energized continuously even when the switch SW1 is opened. A maintenance engineer performs a recovery processing by observing the lamp lit at the alarm display part, and by depressing a switch SW2 when the processing is completed, the relay 22 is recovered, and next, the relay 24 is recovered, then, the lamp at the alarm display part lights out.

66. 发明专利

JPH0260243A BIT STEAL CONTROL SYSTEM 失效
公开(公告)号：JPH0260243A
公开(公告)日：1990-02-28
申请号：JP21193288
申请日：1988-08-25
申请人： FUJITSU LTD
发明人： MIURA NORIHISA , TAKEO HIROSHI , TAKEDA SATOSHI , NAKADE HIROSHI , MATSUSHIMA HIROMASA
IPC分类号： H04J3/00 , H04J3/12
摘要： PURPOSE:To easily control the presence or absence of the insertion of signal bits for respective channel devices by outputting a first control signal from an instruction means in accordance with the presence or absence of a connection means and controlling bit steal based on a second control signal corresponding to the first control signal. CONSTITUTION:A signal bit generation means 121 has the connection means for physically connecting a prescribed section, and removes the connection means 123 when the signal bits are not generated. When the signal bits are generated in the signal bit generation means 121, the instruction means 131 transmits the first control signal 133 for indicating the insertion of the signal bits to a multiplexing means 141 in correspondence with connection by the connection means 123. The multiplexing means 141 supplies the control signal 143 to a data transmission means 111 and the bit generation means 121 in correspondence with the first control signal 133. The data transmission means 111 transmits data and the signal bit generation means 121 outputs the signal bits, whereby data and the signal bits are multiplexed by the multiplex means 141 in correspondence with the second control signal 143.

67. 发明专利

JPH01106638A PCM VOICE CODER/DECODER CIRCUIT 失效
公开(公告)号：JPH01106638A
公开(公告)日：1989-04-24
申请号：JP26409187
申请日：1987-10-20
申请人： FUJITSU LTD
发明人： YAMAZAKI HIROSHI , TAKEO HIROSHI , TAKEDA SATOSHI , NAKADE HIROSHI , MIURA NORIHISA
IPC分类号： H04B14/04 , H04B3/20 , H04M3/18
摘要： PURPOSE:To prevent the oscillation of a voice channel circuit by changing over by throwing a switch to the position of a band pass filter blocking only the oscillated frequency component in detecting the oscillated frequency component. CONSTITUTION:The 1st band rejection filter 91 eliminating only the oscillated frequency and a band pass filter 92 passing only the oscillated frequency are added to an output of a coder 40 in a device using a PCM coder 40/decoder. The oscillated frequency is given to a detecting means 95 through the filter 92, where the oscillated frequency is detected to output a control signal. The control signal is fed to a switch means 96, which is thrown to the position of the output of the filter 91. As a result, the oscillated frequency is blocked by the filter 91 to stop the oscillation. In a conventional speech state, the oscillated frequency is detected by the means 95 through the 2nd and rejection filter 93 blocking only the oscillated frequency component, the means 95 gives the control signal to the means 96, which is thrown to the position to bypass the filter 91. Then the circuitry is restored to the normal operation.

68. 发明专利

JPS63262938A FAST SYNCHRONIZATION CIRCUIT 失效
公开(公告)号：JPS63262938A
公开(公告)日：1988-10-31
申请号：JP9773187
申请日：1987-04-20
申请人： FUJITSU LTD
发明人： TAKEDA SATOSHI , TAKEO HIROSHI , NAKADE HIROSHI , YAMAZAKI HIROSHI , MIURA NORIHISA
IPC分类号： H04J3/06 , H04L7/08 , H04L13/10 , H04L25/40
摘要： PURPOSE:To secure a system which takes out output data in a form of parallel signal and aligns the phase of the parallel signal to be outputted, that is, TSSI (Time Slot Sequence Integrity), by delaying an inputted serial digital signal by a prescribed number of bits by a variable length shift register provided at the front step of a serial-parallel conversion circuit. CONSTITUTION:A frame synchronization pattern is detected from either plural frame synchronization pattern detection circuits (300-1-300-n) provided in parallel, and the position of the pattern at parallel arrangement is detected by a synchronizing position detecting means 600. Corresponding to the above, a control signal which delays an input signal so as to set a frame synchronizing signal at the beginning of the parallel arrangement is added on a signal delay means 500, and the signal delay means 500 delays the input signal by the number of bits decided by the control signal. In such a way, the frame synchronizing signal is set at the forefront of the parallel output of the serial-parallel conversion circuit 200, and no mixing of the data of a preceding and a succeeding frames can be prevented from occurring, and also, the TSSI can be secured.

69. 发明专利

JPS6370633A SYNCHRONIZING PATTERN DETECTOR 失效
公开(公告)号：JPS6370633A
公开(公告)日：1988-03-30
申请号：JP21645586
申请日：1986-09-12
申请人： FUJITSU LTD
发明人： TAKEO HIROSHI , OHATA MICHINOBU , TAKEDA SATOSHI , YAMAZAKI HIROSHI
IPC分类号： H04L7/08
摘要： PURPOSE:To reduce power consumption and to facilitate the constitution of circuits by providing a serial/parallel conversion circuit converting a serial digital signal into a parallel signal by bits each and a frame synchronizing pattern detection circuit applying multi-point detection. CONSTITUTION:A serial digital signal from a transmission line 1 is inputted to a shift register 21 of a serial/parallel conversion circuit 2, the register 21 converts the input signal into p-bit (p=8) parallel signals Q1-Q8, which are outputted to a register 22. A 7th bit signal is outputted from an output section R1 of the register 22, a 6th bit signal is from an output section R2, and signals are outputted similarly from output sections R3-R8. Each 1-bit output from the output sections R1-R8 is inputted to frame synchronizing pattern detection circuits 3-8-3-1 and each circuit is operatable at a low-signal speed 1/8 of that of a serial digital signal. Then multi-point detection of a synchronizing pulse of consecutive 8 frames is applied. Thus, the circuits 3-1-3-8 are constituted by low-speed circuit elements, the power consumption is reduced and the circuit constitution is facilitated.

70. 发明专利

JPS62110322A SAMPLE-AND-HOLD SYSTEM 失效
公开(公告)号：JPS62110322A
公开(公告)日：1987-05-21
申请号：JP25025485
申请日：1985-11-08
申请人： FUJITSU LTD
发明人： TAKEDA SATOSHI , OHATA MICHINOBU , TAKEO HIROSHI , NAKADE HIROSHI , YAMAZAKI HIROSHI
IPC分类号： H03M1/12
摘要： PURPOSE:To double the cycle time for one sample-and-hold and to attain analog/ digital conversion with high speed and good stability by providing two sample- and-hold circuits to one A/D converter and using the two sample-and-hold circuits while being switched in time division. CONSTITUTION:An analog signal is inputted to the sample-and-hold circuit, the signal is traced by sampling and the input signal is subjected to holding. In the constitution shown in figure, the two sample-and-hold circuits No.1, No.2 are provided and the two circuits are used while being switched in time division. Since the two sample-and-hold circuits are used in time division, the sufficient sampling time is obtained and the sampling period is quickened as fast as two times of a conventional period.

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