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51. 发明专利

JP3920443B2 A / d conversion circuit 失效
公开(公告)号：JP3920443B2
公开(公告)日：2007-05-30
申请号：JP4764498
申请日：1998-02-27
申请人：株式会社ルネサステクノロジ
发明人：隆博三木 , 正雄伊藤 , 浩史小紫 , 敏夫熊本 , 毅重信
IPC分类号： H03M1/14 , H03M1/20 , H03M1/36
CPC分类号： H03M1/205 , H03M1/141

52. 发明专利

JP2007124611A Inverter-based flash analog-to-digital converter using floating resistor ladder 审中-公开
标题翻译：基于逆变器的FLASH模拟数字转换器使用浮动电阻梯
公开(公告)号：JP2007124611A
公开(公告)日：2007-05-17
申请号：JP2006127491
申请日：2006-05-01
申请人： Ind Technol Res Inst , インダストリアル・テクノロジー・リサーチ・インスティテュートIndustrial Technology Research Institute
发明人： CHEN CHUN-CHI , LI DAY-UEI
IPC分类号： H03M1/36 , H03K5/08
CPC分类号： H03M1/363
摘要： PROBLEM TO BE SOLVED: To solve a problem that it is desired to have a flash analog-to-digital converter ADC which keeps features of an inverter-based flash ADC such as low power consumption and instructs inverter mismatching without changing inverter sizes or parameters.
SOLUTION: The present invention relates to an A/D converter device for converting an analog signal into a digital signal, and the A/D converter includes a comparator array including a plurality of comparators, each of the comparators including a first inverter and a second inverter connected in series with the first inverter, a resistor string including a plurality of resistors connected in series, each of the resistors corresponding to one of the plurality of comparators, and a current generator for providing a constant current flowing through the resistor string.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了解决需要具有闪存模数转换器ADC的问题，其保持诸如低功耗的基于逆变器的闪存ADC的特征，并指示变频器不匹配而不改变逆变器尺寸或参数。解决方案：本发明涉及一种用于将模拟信号转换为数字信号的A / D转换器装置，并且A / D转换器包括具有多个比较器的比较器阵列，每个比较器包括第一反相器以及与所述第一反相器串联连接的第二反相器，包括串联连接的多个电阻器的电阻串，每个所述电阻器对应于所述多个比较器之一，以及电流发生器，用于提供流过所述电阻器的恒定电流串。版权所有（C）2007，JPO＆INPIT

53. 发明专利

JP3907633B2 Nic circuit and adc circuit 有权
公开(公告)号：JP3907633B2
公开(公告)日：2007-04-18
申请号：JP2004095013
申请日：2004-03-29
申请人：株式会社半導体理工学研究センター
发明人：隆英佐藤 , 浩司坂田 , 博之岡田 , 安行橋本 , 信生藤井 , 茂孝高木
IPC分类号： H03H11/44 , H03M1/36

54. 发明专利

JP3887489B2 The reference voltage generation circuit 失效
公开(公告)号：JP3887489B2
公开(公告)日：2007-02-28
申请号：JP16883298
申请日：1998-06-16
申请人：富士通株式会社
发明人：克義山本 , 寿孝水口
IPC分类号： H03M1/74 , H03G5/16 , H03M1/14 , H03M1/36 , H03M1/46 , H03M1/68 , H03M1/76
CPC分类号： H03M1/685 , H03M1/142 , H03M1/365 , H03M1/765

55. 发明专利

JP2006333185A A/d conversion circuit, a/d converter and sampling clock skew adjusting method 有权
标题翻译： A / D转换电路，A / D转换器和采样时钟调整方法
公开(公告)号：JP2006333185A
公开(公告)日：2006-12-07
申请号：JP2005155226
申请日：2005-05-27
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： NOGUCHI SHIGESANE
IPC分类号： H03M1/10 , H03M1/36
CPC分类号： H03M1/0836 , H03M1/365
摘要： PROBLEM TO BE SOLVED: To provide a high-accuracy A/D conversion circuit with a higher speed as control is performed so as to make skew of a clock signal to skew of an analog input signal optimum in accordance with a digital output signal output by the A/D conversion circuit. SOLUTION: A parallel A/D conversion circuit comprises a plurality of comparators for comparing input signals in parallel, input signal wirings for distributing an input signal to the plurality of comparators, and a sampling clock distribution circuit for distributing a sampling clock for sampling the input signal for the plurality of comparators and determining distributing timing of the sampling clock in accordance with a delay of the input signal by the input signal wirings. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有更高速度的高精度A / D转换电路，执行控制，以便使时钟信号偏斜到根据数字输出最佳的模拟输入信号的偏移信号由A / D转换电路输出。解决方案：并行A / D转换电路包括用于并行输入信号的多个比较器，用于将输入信号分配给多个比较器的输入信号布线，以及用于分配采样时钟的采样时钟分配电路，对多个比较器的输入信号进行采样，并根据输入信号布线的输入信号的延迟确定采样时钟的分配定时。版权所有（C）2007，JPO＆INPIT

56. 发明专利

JP2006287305A Voltage comparator 审中-公开
标题翻译：电压比较器
公开(公告)号：JP2006287305A
公开(公告)日：2006-10-19
申请号：JP2005100797
申请日：2005-03-31
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OKAMOTO YOICHI
IPC分类号： H03K5/08 , H03M1/36
摘要： PROBLEM TO BE SOLVED: To provide a voltage comparator capable of starting a positive feedback (latch) operation by quickly responding to a change in a control voltage without causing a malfunction and quickly returning to a differential amplification operation applied to an input voltage for a high speed operation.
SOLUTION: The voltage comparator includes: a differential input circuit 101 for converting externally received differential input voltages Vinp, Vinn into differential currents and providing outputs of them; a latch circuit 103 for applying positive feedback amplification to output voltages Voutn, Voutp; a second switch circuit 105 including MOS transistors 10, 11 connected between the differential input circuit 101 and the latch circuit 103 and each gate of which receives a first control voltage Vc1; and a third switch circuit 106 including a PMOS transistor 12 connected between the second switch circuit 105 and the latch circuit 103 and whose gate receives a second control voltage Vc2 the polarity of which is inverse to that of the first control voltage Vc1.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种电压比较器，其能够通过快速响应控制电压的变化而启动正反馈（锁存）操作，而不会引起故障，并且迅速返回到施加到输入电压的差分放大操作用于高速运行。电压比较器包括：差分输入电路101，用于将外部接收的差分输入电压Vinp，Vinn转换成差分电流并提供它们的输出; 用于对输出电压Voutn，Voutp施加正反馈放大的锁存电路103; 连接在差分输入电路101和锁存电路103之间的MOS晶体管10,11的第二开关电路105，其各栅极接收第一控制电压Vc1; 以及第三开关电路106，其包括连接在第二开关电路105和锁存电路103之间的PMOS晶体管12，其栅极接收极性与第一控制电压Vc1的极性相反的第二控制电压Vc2。版权所有（C）2007，JPO＆INPIT

57. 发明专利

JP3809695B2 Ad converter 失效
公开(公告)号：JP3809695B2
公开(公告)日：2006-08-16
申请号：JP8970397
申请日：1997-04-08
申请人：ソニー株式会社
发明人：禎浩小松
IPC分类号： H03M1/36

58. 发明专利

JP2006165765A Analog-to-digital converter 有权
标题翻译：模拟数字转换器
公开(公告)号：JP2006165765A
公开(公告)日：2006-06-22
申请号：JP2004351249
申请日：2004-12-03
申请人： Rohm Co Ltd , ローム株式会社
发明人： AZAMI JUNICHIRO
IPC分类号： H03M1/14 , H03M1/36
摘要： PROBLEM TO BE SOLVED: To provide an A/D converter the linearity of which is enhanced.
SOLUTION: The A/D converter 100 is provided with a monitor unit 50 in addition to: a reference voltage circuit 30 for generating a reference voltage; a first conversion unit 10 for generating data of high-order bits; a second conversion unit 20 for generating data of low-order bits; and a composite circuit 40. The monitor unit 50 monitors the data Sf of the low-order bits produced by the second conversion unit 20. The monitor unit 50 predicts offsets of comparators CMPc1 to CMPc3 of a first comparison unit 12 from the data of the low-order bits. When the monitor unit 50 monitors the data and the monitoring results in that data Sf' of the low-order bits are included in an upper side overlap range, a first reference voltage generating section 32 shifts a dense reference voltage Vrc toward a lower voltage, and when the monitoring results in that the data Sf' of the low-order bits are included in a lower side overlap range, the first reference voltage generating section 32 shifts a dense reference voltage Vrc toward a higher voltage.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种A / D转换器，其线性度得到提高。解决方案：除了用于产生参考电压的参考电压电路30之外，A / D转换器100还设置有监视器单元50。用于产生高位数据的第一转换单元10; 用于产生低位数据的第二转换单元20; 和复合电路40.监视器单元50监视由第二转换单元20产生的低位的数据Sf。监视器单元50预测第一比较单元12的比较器CMPc1至CMPc3的偏移量与低位位。当监视器单元50监视数据和监视结果时，低位的数据Sf'包括在上侧重叠范围内，第一参考电压产生部分32将致密的参考电压Vrc移向较低的电压，并且当监视结果将低位的数据Sf'包括在下侧重叠范围中时，第一参考电压产生部分32将致密基准电压Vrc移向较高电压。版权所有（C）2006，JPO＆NCIPI

59. 发明专利

JP3756638B2 Encoder, an error correction method of encoding a signal, a / d-converter, and a / d-converter the test method 失效
公开(公告)号：JP3756638B2
公开(公告)日：2006-03-15
申请号：JP24137697
申请日：1997-09-05
申请人：富士通株式会社
发明人：三六塚本
IPC分类号： H03M1/10 , H03M1/36 , H03M7/16 , H03M13/00

60. 发明专利

JP2005286516A Nic circuit and adc circuit 有权
标题翻译：网卡电路和ADC电路
公开(公告)号：JP2005286516A
公开(公告)日：2005-10-13
申请号：JP2004095013
申请日：2004-03-29
申请人： Handotai Rikougaku Kenkyu Center:Kk , 株式会社半導体理工学研究センター
发明人： FUJII NOBUO , TAKAGI SHIGETAKA , SATO TAKAHIDE , TAKAHASHI NORIAKI , OKADA HIROYUKI , HASHIMOTO YASUYUKI , SAKATA KOJI
IPC分类号： H03M1/36 , H03H11/44
摘要： PROBLEM TO BE SOLVED: To realize an NIC circuit which easily realizes stable operating conditions.
SOLUTION: The NIC circuit comprises a first current route with constant current sources 21, 22 connected in series to a transistor M1, and a second current route formed symmetrically to the first current route with constant current sources 23, 24 connected in series to a transistor M2. One differential input signal Vsig 1 is inputted to the control terminal of M2 via a first buffer B1, and connected to a connection node of the constant current source 21 and M1 via a second buffer B2, and the other differential input signal Vsig 2 is inputted to the control terminal of M1 via a third buffer B3 and connected to a connection node of the constant current source 23 and M2 via a fourth buffer B4.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：实现容易实现稳定工作条件的NIC电路。解决方案：NIC电路包括具有与晶体管M1串联连接的恒定电流源21,22的第一电流路径以及与第一电流路径对称地形成的第二电流路径，其中恒定电流源23,24串联连接到晶体管M2。一个差分输入信号Vsig 1通过第一缓冲器B1输入到M2的控制端，经由第二缓冲器B2连接到恒流源21和M1的连接节点，另一个差分输入信号Vsig 2被输入经由第三缓冲器B3连接到M1的控制端子，并且经由第四缓冲器B4连接到恒流源23和M2的连接节点。版权所有（C）2006，JPO＆NCIPI

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