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51. 发明专利

JPH0257348B2 失效
公开(公告)号：JPH0257348B2
公开(公告)日：1990-12-04
申请号：JP25728585
申请日：1985-11-15
申请人： HANDOTAI KENKYU SHINKOKAI
发明人： NISHIZAWA JUNICHI , TAMAMUSHI NAOSHIGE , NONAKA KENICHI
IPC分类号： H01L29/80 , H01L21/332 , H01L29/739 , H01L29/74

52. 发明专利

JPH02291171A GATE TURN-OFF THYRISTOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH02291171A
公开(公告)日：1990-11-30
申请号：JP5682090
申请日：1990-03-09
申请人： SIEMENS AG
发明人： KURAUSUGIYUNTAA OTSUPERUMAN
IPC分类号： H01L29/74 , H01L21/18 , H01L21/332 , H01L29/10 , H03K17/732
摘要： PURPOSE: To reduce loss of electric power, caused by carrier carrying-out by performing taking out of an excessive carrier accumulating in the first base layer under conduction state of thyristor chiefly through a part layer of the first base layer which is very strongly doped. CONSTITUTION: A semiconductor block comprises an n -doped n-emitter 1, a p -doped p-base 2, an n -doped n-base 3, a p -doped p-emitter 4, and a positive pole side electrode 5 comprising a terminal A, formed of such conductive material as aluminum. The n-base 3 extends as far as a first main surface 12 of a thyristor, surrounding the side surface of the p-base layer 2 extending as far as the main surface 12. A thin part layer 21, present at the n-base 3, which is strongly n -doped extends as far as a side edge 22 of the semiconductor block, to contact to a conductive coat 23 there. The conductive coat 23 extends to a main surface 12 from the side edge 22 to the main surface 22, comprising a terminal 24 within a range of the main surface 12. This is connected, through a switch 25, to a negative pole of a DC voltage source 26, with a positive pole connected to a terminal A. The switch 25 is a field effect transistor, and its gate is provided with a terminal 27.

53. 发明专利

JPH02197169A GATE TURN OFF THYRISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02197169A
公开(公告)日：1990-08-03
申请号：JP1683089
申请日：1989-01-26
申请人： NIPPON INTER ELECTRONICS CORP
发明人： SAKAMOTO HIROAKI
IPC分类号： H01L29/74 , H01L21/332 , H01L29/744
摘要： PURPOSE:To shorten a gate turn off thyristor of this design in turn-off time by a method wherein the PE layer of a GTO is made low in impurity concentration so as to restrain holes from injecting from the PE layer. CONSTITUTION:An N-type substrate 1 is subjected to a wet oxidation, and a P thin layer 11 is formed using H2+Ga2O3. One side of the substrate 1 is etched and B is diffused to form a P layer 11b. Next, the same as a conventional one, P is diffused from the upside of the P layer 11b to selectively form an anode shortcircuiting N layer 12. Then, P is driven in to form a P layer 11c and an N layer 12a of specified thicknesses. An N layer serving as an electrode is diffused into another primary face cf a P layer 11c, and a four- layered structure composed of an NE layer 13, a PB layer 14, an NB layer 15, a PE layer 16a, and an NS layer 17 can be obtained. Next. the NE layer 13 is selectively etched to be formed into an island-like NE layer, and an electrode is provided to these layers respectively to complete the formation of a GTO. As a PE layer is small in impurity concentration, holes are restrained from injecting from the PE layer at turn-off and a GTO of this design can be made especially short in turn-off time.

54. 发明专利

JPS6466965A GATE TURN-OFF THYRISTOR 失效
公开(公告)号：JPS6466965A
公开(公告)日：1989-03-13
申请号：JP19780288
申请日：1988-08-08
申请人： ASEA BROWN BOVERI
发明人： PEETAA ROTSUGUBUIIRERU , TOOMASU FURAZAKU , YAN FUOBORIRU
IPC分类号： H01L29/74 , H01L21/225 , H01L21/332 , H01L29/06 , H01L29/10 , H01L29/744
摘要： PURPOSE: To surely control high break voltage by arranging the junction part of a thyristor in a p-type base center layer region, and arranging a negative incline in the p-type base insulating region, and crossing it with the pn-junction composed of a p-type base insulating layer and an n-type base layer. CONSTITUTION: A first deposition layer 2 is made of aluminum at a semiconductor substrate 1, doped with n-type impurities. After etching, a second deposition layer 3 is formed over the entire surface after etching and is dispersed, whereupon aluminum of a high dispersion constant is positioned deep, and this makes a p-type base insulating layer 5, and boron makes a p-type base center layer 4. After formation of a p-type emitter layer 8 and a gate cathode structure 11, a negative slope 6 is imparted to it by sand jet or polishing. It is desirable that the thickness of the center layer 4 be smaller than 70μm, and that the thickness of the p-type base insulating layer 5 be larger than 90μm.

55. 发明专利

JPS6155786B2 失效
公开(公告)号：JPS6155786B2
公开(公告)日：1986-11-29
申请号：JP11761579
申请日：1979-09-12
申请人： MITSUBISHI ELECTRIC CORP
发明人： SADAMORI MASAAKI
IPC分类号： H01L29/74 , H01L21/332

56. 发明专利

JPS61158179A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61158179A
公开(公告)日：1986-07-17
申请号：JP27872684
申请日：1984-12-28
申请人： TOSHIBA CORP , TOSHIBA COMPONENT KK
发明人： YAKUSHIJI SHIGENORI , MATSUMOTO SHINICHI
IPC分类号： H01L29/74 , H01L21/332 , H01L29/747
摘要： PURPOSE:To equip a device with high sensitivity in its gate trigger feature under the III(+) mode by a method wherein a third surface layer is formed on the ground surface to partially overlap the portion just under a first surface layer and a second intermediate layer adjoining the third surface layer at the side of the first surface layer is made to be lower in impurity concentration than a second intermediate layer exposed portion adjoining the third surface layer. CONSTITUTION:A first intermediate layer adjoining a TRIAC first surface layer NE1 at the side of a third surface layer NE2 is lower in impurity concentration and shallower in depth of diffusion than a first intermediate layer exposed portion P1 adjoining the first, second surface layers NE1, NE2. A second intermediate layer adjoining a thirs surface layer NE2 at the side of the first surface layer NE1 is lower in impurity concentration and shallower in depth of diffusion that a second intermediate layer exposed portion P2. On the surface of the substrate, a first main electrode T1 and gate electrode G are provided, respectively bridging the first surface layer NE1 or second surface layer NEG and the first intermedaite layer exposed portion P1 and, on the other surface of the substrate, a second main electrode T2 is provided, bridging the thirs surface layer NE2 and second intermediate layer exposed portion P2.

57. 发明专利

JPS59151461A Manufacture of hetero junction thyristor 失效
标题翻译：异相接头制造商的制造
公开(公告)号：JPS59151461A
公开(公告)日：1984-08-29
申请号：JP2380083
申请日：1983-02-17
申请人： Oki Electric Ind Co Ltd
发明人： ARAI MICHIHIKO , FURUKAWA RIYOUZOU
IPC分类号： H01L21/20 , H01L21/332 , H01L29/74
CPC分类号： H01L29/74
摘要： PURPOSE:To obtain a hetero junction thyristor of high performance through simple manufacture by diffusing only one of p type or n type impurities to a hetero junction epitaxial layer. CONSTITUTION:There is an n type high-concentration substrate material n layer in depth deeper than D3 in a substrate. On the other hand, a low-concentration n type epitaxial layer n1 layer is crystal-grown between D2 and D3 on said layer, a high-concentration n type epitaxial layer n layer between D1 and D2 on the n1 layer and a low-concentration n type epitaxial layer n2 layer between D0 and D1 on the n layer. Such epitaxial growth is executed, and a p type impurity is diffused in N4 surface concentration from the surface D0. p Type concentration is made larger than others in the n2 layer between D0 and D1 and the n1 layer between D2 and D3 and p type concentration is made smaller than others in the n layer between D1 and D2 as necessary conditions for p type impurity concentration at that time. According to such diffusion, a p-n- p-n type junction is obtained through one-time diffusion process. Consequently, there is no pollution of impurities among each layer because the same type epitaxial growth is used, and each layer can be acquired by one-time growth, thus obtaining excellent characteristics.
摘要翻译：目的：通过将p型或n型杂质中的一种仅扩散到异质结外延层，通过简单的制造获得高性能的异质结晶闸管。构成：在衬底中存在深度比D3深的n型高浓度衬底材料n +层。另一方面，低浓度n型外延层n1层在所述层上的D2和D3之间晶体生长，n1上的D1和D2之间的高浓度n型外延层n + 层和n +层之间的D0和D1之间的低浓度n型外延层n2 - 层。执行这种外延生长，并且p型杂质从表面D0扩散到N4表面浓度。在D1和D2之间的n +层中，在D2和D3之间的n2层和D2和D3之间的n2层中，p型浓度大于其他n2层，并且在D1和D2之间的n +层中p型浓度小于其他浓度作为此时p型杂质浓度的必要条件。根据这种扩散，通过一次性扩散过程获得p-n-p-n型结。因此，由于使用相同型的外延生长，因此在各层中不会有杂质污染，可以通过一次生长获得各层，从而获得优异的特性。

58. 发明专利

JPS5919322B2 JPS5919322B2 - 失效
公开(公告)号：JPS5919322B2
公开(公告)日：1984-05-04
申请号：JP6056678
申请日：1978-05-23
申请人： Nippon Kogaku Kk
发明人： MIURA SHINJI
IPC分类号： G02B7/08 , G02B7/04 , G02B21/00 , G02B21/24 , H01L21/332

59. 发明专利

JPS57181164A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS57181164A
公开(公告)日：1982-11-08
申请号：JP6904382
申请日：1982-04-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAMAGAMI KOUZOU
IPC分类号： H01L29/73 , H01L21/331 , H01L21/332 , H01L29/74
摘要： PURPOSE:To facilitate the assembly for high reliability, by forming inversion type isolated regions by selective diffusion from windows of insulating films provided on both surfaces of a substrate and then forming each region for cutting in mesa type control rectifying elements. CONSTITUTION:Lattice windows facing to each other are provided on SiO2 films provided on upper and lower surfaces of an N type Si substrate 1 to selectively diffuse P type impurity therefrom being joined at the center to form a P type isolated region 11. After the removal of the SiO2 film on the both surfaces, P type diffused layers 2, 3 are formed further to form an N type emitter layer 4. Next, a mesa etched groove 6 reaching the first base layer 1 deeper than junction J2 is formed, which is cut at the point of the P type isolated region 11 into individual pellets for a mesa type control rectifying element. This method allows easy assembly and stable insulating films of the junction to enhance reliability.

60. 发明专利

JPS54153046A INVESTIGATING SPEED CONTROLLER FOR OPTICAL MACHINE 失效
公开(公告)号：JPS54153046A
公开(公告)日：1979-12-01
申请号：JP6056678
申请日：1978-05-23
申请人： NIPPON CHEMICAL IND
发明人： MIURA SHINJI
IPC分类号： G02B7/08 , G02B7/04 , G02B21/00 , G02B21/24 , H01L21/332

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