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51. 发明专利

JPH08306678A MANUFACTURE OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08306678A
公开(公告)日：1996-11-22
申请号：JP10958595
申请日：1995-05-08
申请人： HITACHI LTD
发明人： MIURA HIDEO , IKEDA SHUJI , SUZUKI NORIO , SAITO NAOTO , NISHIMURA ASAO
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
摘要： PURPOSE: To reduce fully the effect of bird's beak regions and to make it possible to flatten fully the exposed surface of a silicon substrate. CONSTITUTION: A pad film 2 is formed on the surface of a silicon substrate 1 using a thermal oxidation method and thereafter, a silicon nitride film 3 is deposited on the film 2. Then, the film 3 on a region which wants to finally form thick an element isolation oxide film is removed by etching, an aperture 20 is formed to make the film 2 expose and thereafter, the substrate 1 is selectively oxidized via the aperture 20 by the thermal oxidation method to form a thick silicon oxide film 4 and the film 3 is removed. Moreover, after the entire surface of the film 4 is again subjected to additional oxidation in a state that the film 4 or bird's beaks 4A is or are exposed, the whole film 4 is removed by a prescribed thickness from its upper part for removing the unnecessary film 4 formed on the periphery of the film 4 to form the element isolation oxide film 4B.

52. 发明专利

JPH08213478A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08213478A
公开(公告)日：1996-08-20
申请号：JP8231595
申请日：1995-04-07
申请人： HITACHI LTD
发明人： SHIRASU TATSUMI , KIYOTA SHOGO , KUBO SEIJI , OKUYAMA KOSUKE , SUZUKI NORIO
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/205
摘要： PURPOSE: To improve setting accuracy in element characteristics by forming a specified element on an epitaxial layer of a low impurity concentration provided on the first and second semiconductor areas of high impurity concentration. CONSTITUTION: On wells 3a and 3b of high impurity concentration, an epitaxial layer 2E of low impurity concentration is provided, and on the epitaxial layers 2E1 and 2E2. pMOS5P and nMOS5N are formed. Into the epitaxial layer 2E1 on the well 3a, for example, phosphorus of n-type impurity, is introduced. Into the epitaxial layer 2E2 on the well 3b, for example, boron of p-type impurity, is introduced. By this, characteristics of the pNOS 5P and nMOS 5N (threshold voltage, substrate effect, etc.) are set with high accuracy without affected by impurities of the wells 3a and 3b and a semiconductor substrate body 2S, so setting accuracy of the characteristics is improved.

53. 发明专利

JPH07211803A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH07211803A
公开(公告)日：1995-08-11
申请号：JP29416894
申请日：1994-11-29
申请人： HITACHI LTD
发明人： MEGURO SATOSHI , UCHIBORI KIYOBUMI , SUZUKI NORIO , MOTOYOSHI MAKOTO , KOIKE ATSUYOSHI
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To increase the level of integration of an SRAM, by constituting a node by electrically connecting the gate electrode of an MISFET for driving with the source region or the drain region of an MISFET for transferring, and connecting the gate electrode or the drain electrode of an MISFET for load with the node. CONSTITUTION:The gate electrode 14 of an MISFET Qp1 for load is connected with a semiconductor region 11 as the drain region of an MISFET Qd2 for driving, via a gate electrode 7. Similarly the gate electrode 14 of an MISFET Qp2 for load is formed so as to cover the upper part of the gate electrode 7 of the MISFET Qd2 for driving. The sate electrode 14 of the MISFET Qp2 for load is connected with the semiconductor region 11 as the drain region of the MISFET Qd1 for driving which region is constituted in an unified body with the one side semiconductor region 11 of an MISFET Qt2 for transferring. Thereby the level of integration is improved, the power consumption is reduced, the load element of a memory cell is optimized, and the soft error is prevented.

54. 发明专利

JPH0689862A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0689862A
公开(公告)日：1994-03-29
申请号：JP23939192
申请日：1992-09-08
申请人： HITACHI LTD
发明人： YOSHIZAWA MIYOSHI , HIRAIWA ATSUSHI , KOBAYASHI TAKASHI , YOSHIGAMI JIRO , SHIMIZU HIROBUMI , KOIKE ATSUYOSHI , SUZUKI NORIO , KATO HISAYUKI , NAKAMURA HITOSHI , KAWAMURA TAKESHI , KANEMITSU KENJI
IPC分类号： H01L21/205
摘要： PURPOSE:To manufacture a semiconductor device wherein the defect density is reduced for a gate insulating film of a MOS transistor having a doped silicon film as a gate electrode. CONSTITUTION:A doped silicon film 104 is formed on a gate oxide film 103 at a temperature of 460-500 deg.C or 540-700 deg.C followed by heat treatment of the doped silicon film 104 at a temperature of 650-1100 deg.C, or the doped silicon film 104 is formed at a temperature between 500 deg.C and 540 deg.C followed by heat treatment of the doped silicon film 104 at a temperature of 650-900 deg.C in order to make this doped silicon film 104 a gate electrode 106.

55. 发明专利

JPH0564458B2 失效
公开(公告)号：JPH0564458B2
公开(公告)日：1993-09-14
申请号：JP8941584
申请日：1984-05-07
申请人： HITACHI LTD
发明人： KOMORI KAZUHIRO , OKUYAMA KOSUKE , SUZUKI NORIO , KATSUTO HISAO
IPC分类号： H01L27/08 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/78 , H01L29/784

56. 发明专利

JPH01233739A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01233739A
公开(公告)日：1989-09-19
申请号：JP6171888
申请日：1988-03-14
申请人： HITACHI LTD
发明人： KOJIMA MASAYUKI , KIGUCHI YASUO , NISHIHARA SHINJI , SUZUKI NORIO , KOIKE ATSUYOSHI
IPC分类号： H01L21/3213 , H01L21/027 , H01L21/30 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To prevent a halation and to enhance the position detection accuracy of an electrode by a method wherein an Al film and a conductive film which is composed of a conductive material whose light reflectance is lower than that of Al are applied one after another to the surface of an insulating film, a wiring pattern is formed and one part of the conductive film of the wiring pattern is removed. CONSTITUTION:An insulating film 2 is formed on a wafer 1. After an Al film 3 has been applied to the surface of the insulating film 2, a silicide film 4 is applied to the surface of the Al film 3. By patterning the Al film 3 and the silicide film 4, a first-layer wiring part 5 composed of a two-layer structure is formed. The wiring part 5 is annealed. A PSG film 6 is applied to the surface of the wafer 1; after an SOG film 7 has been coated on its surface by using a spinner, the SOG film 7 is flattened. After an interlayer connection hole reaching the wiring part 5 has been made, a second-layer wiring part 8 composed of the Al film 3 and the silicide film 4 is formed. Only the silicide layer 4 at an upper layer is removed; the Al film 3 is exposed. By this setup, a halation can be prevented; the position detection accuracy of an electrode can be enhanced.

57. 发明专利

JPS6419489A HANDWRITTEN CHARACTER INPUT DEVICE 失效
公开(公告)号：JPS6419489A
公开(公告)日：1989-01-23
申请号：JP17462887
申请日：1987-07-15
申请人： HITACHI LTD , HITACHI CHUBU SOFTWARE KK
发明人： KONISHI YOSHIHARU , SUZUKI NORIO , MATSUDA TOSHIHIKO , HAYASHI TAKAHIDE
IPC分类号： G06K9/62 , G06K9/03 , G06K9/68
摘要： PURPOSE:To easily input both character styles of an old KANJI (Chinese character) and a KANJI in common use, by inputting a known character, and converting it to the other character style, even when an operator knows only one of the old KANJI and the KANJI in common use. CONSTITUTION:A character code converting part 15 consists of a character recognizing part 6 for analyzing a coordinate data from a tablet 1 and recognizing a character, etc., a memory 7 for storing a dictionary for recognizing its character, an old KANJI/KANJI-in-common use converting part 8, a memory 9 for storing its conversion table, and a character style selecting part 10 for displaying the old KANJI on a CRT 16 and selecting a character style outputted to the outside. In this state, with respect to a KANJI character code which is recognized by a handwriting input to a device, the corresponding old KANJI, and the corresponding KANJI in common use are displayed in case of the KANJI in common use in which the old KANJI exists, and in case of the old KANJI, respectively, and it is selected by an operator. In such a way, even when the operator knows only one character style of the KANJI in common use and the old KANJI, the other character style can be easily inputted and the input efficiency is improved.

58. 发明专利

JPS62249474A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62249474A
公开(公告)日：1987-10-30
申请号：JP9205186
申请日：1986-04-23
申请人： HITACHI LTD
发明人： IKEDA SHUJI , MEGURO SATOSHI , SUZUKI NORIO
IPC分类号： H01L27/11 , G11C11/34 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/088 , H01L27/10 , H01L27/108
摘要： PURPOSE:To increase stored charge and avoid soft errors by a method wherein a high concentration semiconductor region which is brought into contact with the drain region of a driving MISFET and has the conductivity type opposite to that of the drain region is formed below the drain region and the channel forming region of the driving MISFET. CONSTITUTION:The drain region of a driving MISFET (Q) is composed of a semiconductor region 9 which has a deeper junction depth than the source region or the drain region (semiconductor region 11) of a transfer MISFET (Qs) and a high concentration semiconductor region 5 which is brought into contact with the semiconductor region 9 is provided on the main surface of a well region 2 at a deep position below the semiconductor region 9 and a channel forming region. With this constitution, a potential barrier region against minority carriers created by alpha-ray can be formed without inducing fluctuation in threshold of the driving MISFET (Q) and, at the same time, the capacity of the p-n junction composed of the high concentration semiconductor region 5 and the high concentration semiconductor region 9 can be increased. Therefore, penetration of minority carriers into an information storing capacity C is avoided while electrical reliability at the time of information writing is being improved.

59. 发明专利

JPS62241369A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62241369A
公开(公告)日：1987-10-22
申请号：JP8411686
申请日：1986-04-14
申请人： HITACHI LTD
发明人： KOMORI KAZUHIRO , SUZUKI NORIO
IPC分类号： G11C11/41 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PURPOSE:To prevent the voltage drop of a node, and to improve the holding characteristics of an information by connecting a first conductivity type MISFET and a resistance element consisting of an silicon film constituted on an insulating film through an intermediate layer having a softening point higher than the temperature of heat treatment of the silicon film and conductivity. CONSTITUTION:Conductive intermediate layers 12 such as TiN (titanium nitride) films are formed in two connecting holes 10 for connecting a conductive layer 11 integrally shaped with a resistance element R1 or R2 and each gate electrode 5 for drive MISFETs QD1 and QD2, and p-n junctions are formed among the conductive layer 11 composed of a p-type polycrystalline silicon film and the gate electrodes 5 made up of n-type polycrystalline silicon films. That is, the conductive layer 11 is connected to the conductive intermediate layers 12, and the conductive intermediate layers 12 are connected to the gate electrodes 5, thus ohmic-connecting the conductive layer 11 and the gate electrodes 5, then preventing the lowering of the potential of nodes, n type semiconductor regions 6, 7 as drain regions in the drive MISFET QD1 or the drive MISFET QD2.

60. 发明专利

JPS6281732A METHOD FOR SMOOTHENING INSULATING FILM 失效
公开(公告)号：JPS6281732A
公开(公告)日：1987-04-15
申请号：JP22181585
申请日：1985-10-07
申请人： HITACHI LTD
发明人： SUZUKI NORIO , KOIKE ATSUYOSHI , KOJIMA MASAYUKI , NAGAI AKIRA , MEGURO SATOSHI , NAGASAWA KOICHI
IPC分类号： H01L21/3205 , H01L21/31
摘要： PURPOSE:To form a smooth insulating film on the wiring as well as to make the film thickness of the insulating film on the wiring constant by forming a first insulating film on the wiring, forming a first film of flow property and smoothening the surface thereof, thereafter performing etching back until the wiring surface is exposed, and forming a second insulating film. CONSTITUTION:A first-layer Al wiring 3 is formed on the insulating film 2 of the semiconductor substrate 1 surface, then, thereon a silicon oxide film 4 as a first insulating film is formed, and further a spin-on glass film 5 as a film of flow property is formed. At this time, the spin-on glass film 5 is formed by one-time coating of spin-on glass, and the surface thereof is planarized. Then, under the condition that the etching selection ratio of the spin-on glass film 5 and the silicon oxide film 4 is substantially 1, etching back is performed by means of the reactive ion etching method until the surface of each Al wiring 3 is exposed, thereby forming a spacer 6. In this case, the Al wiring 3 functions as an etching stopper, and the surface is smoothened by said etching-back. Thereafter, a silicon oxide film 7 as a second insulating film is formed.

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