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51. 发明专利

JPS63236159A MEMORY ACCESS SYSTEM FOR PARALLEL PROCESSOR 失效
公开(公告)号：JPS63236159A
公开(公告)日：1988-10-03
申请号：JP6881287
申请日：1987-03-25
申请人： HITACHI LTD
发明人： NAKAKOSHI JUNJI , HAMANAKA NAOKI , OMODA KOICHIRO , TANAKA TERUO , NAGASHIMA SHIGEO , OSHIMA KAZUO
IPC分类号： G06F15/167 , G06F13/18
摘要： PURPOSE:To decrease sync information given to a memory controller by securing a multi-stage constitution of a priority circuit to hold partly the sync information in response to the priority circuit and allocating the data read out of a memory according to the decoding result of the sync information to send these data to be processors that transmitted the requests. CONSTITUTION:A means 1 is provided to hold the requests for main memory MS received from each processor element PE together with a means 2 which gathers at least >=2 means 1 to decide the priority, a means 3 which holds several bits of the sync information in case the MS request whose priority is decided by the means 2 is equal to an MS reading request, and a means 4 which extracts a single piece of sync information on the means 3 every time the data read out of the MS is transferred and decides the receiver of said data. These means are arranged in a multi-stage constitution. In such a way, the quantity of the sync information given to a memory controller can be decreased despite several 1,000-10,000 pieces of processors.

52. 发明专利

JPS63223857A PARALLEL PROCESSOR 失效
公开(公告)号：JPS63223857A
公开(公告)日：1988-09-19
申请号：JP5650787
申请日：1987-03-13
申请人： HITACHI LTD
发明人： TANAKA TERUO , HAMANAKA NAOKI , OMODA KOICHIRO , NAKAKOSHI JUNJI , OSHIMA KAZUO , NAGASHIMA SHIGEO
IPC分类号： G06F15/173 , G06F9/44 , G06F15/17 , G06F15/80
摘要： PURPOSE:To know a process requiring presently reception data and the reception data desired by the process and to report actively the reception of the desired data to the reception data part by receiving part, by providing a 2nd assosiative memory. CONSTITUTION:A reception buffer (1st associative memory) 8 storing temporarily the identifiers and process numbers is retrieved via a retriever and a process number. If no desired data is obtained, the retriever and the process number are stored in the 2nd associative memory 13. Hereafter the identifier, the process number and the data received successively by a data receiving part in a processor are stored temporarily in the buffer 8. At the same time, the received identifier and the process number are used for retrieval of the memory 13. When the coincident retrievers and process numbers are obtained, a fact that the reception data is received by the reception buffer is informed to an instruction executing part 5.

53. 发明专利

JPS63111562A TRANSFER SYSTEM FOR VECTOR DATA BETWEEN PARALLEL PROCESSORS 失效
公开(公告)号：JPS63111562A
公开(公告)日：1988-05-16
申请号：JP25566386
申请日：1986-10-29
申请人： HITACHI LTD
发明人： NAKAKOSHI JUNJI , TANAKA TERUO , HAMANAKA NAOKI , OMODA KOICHIRO , NAGASHIMA SHIGEO
IPC分类号： G06F15/173 , G06F15/16 , G06F17/16
摘要： PURPOSE:To transfer the vector data at a high speed by fetching the transferred vector data directly to a vector register when the vector data is transferred between processors. CONSTITUTION:Each of processors 110-112 contains a data receiving device 120, a data transmitting device 130, a data processor 140 and a local memory 150. The device 120 inputs data packets 102 and 107 received via a data communication channel 101 and decides whether it should receive these packets 102 and 107. Based on the result of said decision, a permission signal is sent to the processor 140 and an instruction is given to a vector register 141 to write the vector data.

54. 发明专利

JPS6315334A PARALLEL PROCESSOR 失效
公开(公告)号：JPS6315334A
公开(公告)日：1988-01-22
申请号：JP15781886
申请日：1986-07-07
申请人： HITACHI LTD
发明人： OMODA KOICHIRO , NAKAKOSHI JUNJI , NAGASHIMA SHIGEO , TANAKA TERUO , HAMANAKA NAOKI
IPC分类号： G06F15/16 , G06F9/38 , G06F15/177
摘要： PURPOSE:To attain the reallocation of a processing to another processor possible to operate when a processor is placed under a state impossible to operate, by inputting information from a first and a second holding means, detecting the number of the processor to which the processing can be allocated, and performing the allocation of the processing to each processor. CONSTITUTION:The processing read out from a memory device by a reading means is allocated to and executed at each processor, and at this time, a detecting means sends the number of the processor in which no fault is found, and which is not operated at present, to an allocating means, based on the state of the processor held in the first and the second holding means. The allocating means allocates the processing sequentially based on the number of the processor. Also, when the second holding means in execution on the processor, is set at a state impossible to start up, the detecting means detects the number of the processor, and sends it to the allocating means. The allocating means performs the reallocation of the processing based on the number of the processor. In this way, it is possible to allocate the processing dynamically in the execution time of a program, and furthermore, to reallocate the processing when the fault, etc., is found in the processor.

55. 发明专利

JPS61103188A Graphic display unit 失效
公开(公告)号：JPS61103188A
公开(公告)日：1986-05-21
申请号：JP22391384
申请日：1984-10-26
申请人： Hitachi Ltd
发明人： TSUJIOKA SHIGEO , NAKAKOSHI JUNJI
IPC分类号： G06F3/153 , G06F3/14 , G06T11/00 , G09G1/00 , G09G1/16 , G09G5/00 , G09G5/36

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