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    • 51. 发明专利
    • CONTINUITY TEST SYSTEM
    • JPS62268245A
    • 1987-11-20
    • JP11081686
    • 1986-05-16
    • HITACHI LTDNIPPON TELEGRAPH & TELEPHONE
    • KOMATSU AYAFUMISANBE TAKESHI
    • H04M3/26
    • PURPOSE:To eliminate the need for a terminal and the hardware exclusively for the test by providing a loop back setting to the interface section of photoelectric/electrooptic signal conversion and using an idle signal informing the open channel to an opposite transmission equipment so as to conduct the continuity test for the channel. CONSTITUTION:In testing a path 1 between a B.I terminal and an A.O terminal between interface sections SDCA and SDCB of photo electric/electrooptic conversion corresponding to input/output lines, a specific pattern signal from an IDLE is returned to the DET of the IDLE via the path of IDLE (signal device)-T.I terminal-SSW(channel)-B.O terminal-TST loopback of SDCB-B.I terminal-path 1-A.O terminal-TST loopback of SDCA-A.I terminal-SSW T.O terminal-DET (detector) of IDLE so as to discriminate whether or not a normal path is formed. If the path is not normally completed, the path 2 is checked by the DET of the SDCB, the path 1 is checked by the DET of the SDC A and the path 3 is checked by the DET of the IDLE to decide which path is faulty.
    • 53. 发明专利
    • SIGNAL DETECTION SYSTEM
    • JPS6251314A
    • 1987-03-06
    • JP18952985
    • 1985-08-30
    • HITACHI LTD
    • KOMATSU AYAFUMI
    • H03K5/19H03K5/00
    • PURPOSE:To detect simply and surely the absence of a signal with high reliability by not using a common clock source but using an output clock of a clock extraction circuit corresponding to an output interface circuit. CONSTITUTION:A signal reproducing circuit consists of a clock extraction circuit 9 and a D flip-flop 10, a clock signal CLK is extracted from an input signal DATA having waveform distortion and the clock signal subjected to phase control is obtained by applying phase control to a PLL circuit and the waveform distortion is eliminated by using the D flip-flop 10 to cancel the input signal DATA while using the clock and the result is sent to a post-device. On the other hand, an input signal detection circuit 6 detects the presence of the input signal DATA and when it is present, the input signal DATA from the exchange switch 5 is sent as it is to the signal reproducing circuit via a changeover circuit 7, but when no input signal DATA exists, an idle signal from a common idle source 8 is sent to the signal reproducing circuit via a changeover circuit 7.
    • 54. 发明专利
    • SIGNAL TRANSMISSION SYSTEM
    • JPS60152140A
    • 1985-08-10
    • JP715884
    • 1984-01-20
    • HITACHI LTD
    • KOMATSU AYAFUMI
    • H04L1/00H04Q1/24
    • PURPOSE:To verify correct/faulty in the signal line of the entire device without adding any parity line other than required signal lines by applying H/L control to one signal line among transmission data lines used as the parity line to transmit a signal to the reception side. CONSTITUTION:In turning on the switch of an incoming line 16 and an outgoing line 8, an ON/OFF bit is controlled so that the number of Hs of set/reset at 16X 8 cross points and an incoming line selection level signal INLV go to an odd number. If a data line has a fault when the switch of the incoming line 0 and the outgoing line 0 is turned on and if the INLV bit goes from L to H in mistake, the number of Hs of the INLV+ON/OFF bits is an odd number even if the ON/OFF bit is brought into L level to turn on the switch, no switch is turned on. In this case, the fault is found out that the switch path is not closed actually regardless of the turning on the switch.