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51. 发明专利

JPH0619747B2 失效
公开(公告)号：JPH0619747B2
公开(公告)日：1994-03-16
申请号：JP558784
申请日：1984-01-18
申请人： HITACHI LTD
发明人： UMENO HIDENORI , KUBO TAKASHIGE , HAGIWARA NOBUTAKA , SATO HIROAKI , SAWAMOTO HIDEO
IPC分类号： G06F9/455 , G06F9/46 , G06F12/08 , G06F12/10 , G06F13/10
摘要： In a system having a virtual machine system capable of concurrently running at least one operating system (OS) under one real computer system (host system) and a control program (VMCP) for controlling the VMS:… (i) The VMCP is provided with a translation table from a virtual sub-channel number to a real sub-channel number, which is used by an I/O instruction executing microprogram.… (ii) A real sub-channel control block has a VM information area in which the virtual sub-channel numbers and the translated real sub-channel numbers are contained.… (iii) The VM information area of the real sub-channel control block has a status field in which a flag indicating that the subchannel is dedicated to or not is contained. When the flag is "1", it means that the sub-channel is dedicated to the VM and the sub-channel scheduling by the VMCP is not necessary.… (iv) As the real interruption priority order is dedicated to the VM, only the I/O requesting sub-channel of the dedicating VM is queued into the interruption request queue of that priority order, and the mixing of the VM's in that real interruption priority order is avoided. When the interruption control mask of the interruption priority order of the OS on the VM is "0" indicating that the interruption is not acceptable, the interruption control mask of the corresponding real interruption priority order is also "0" and the hardware interruption does not take place. Accordingly, the interruption is retained by the hardware and the I/O interruption retention of the VM by the VMCP is avoided. … In order to support the above system, the types of the real interruption priority orders are increased to allow the VM to dedicate the real interruption priority order.

52. 发明专利

JPH0659919A COMPUTER SYSTEM 失效
公开(公告)号：JPH0659919A
公开(公告)日：1994-03-04
申请号：JP14174793
申请日：1993-06-14
申请人： HITACHI LTD
发明人： UMENO HIDENORI , KUBO TAKASHIGE , HAGIWARA NOBUTAKA , SATO HIROAKI , SAWAMOTO HIDEO
IPC分类号： G06F9/46 , G06F12/10 , G06F13/10
摘要： PURPOSE:To reduce the simulation overhead of a control program by a virtual computer at the time of executing a held interruption inspecting instruction. CONSTITUTION:Information indicating whether each real interruption priority order is occupied by a traveling OS or not is stored in a real interruption priority order register 1045 included in an I/O interruption processing circuit 1040. When an inspection for checking the existence of a held interruption is requested from the traveling OS, the circuit 1040 checks the contents of a real interruption holding register 1042' by means of the registers 1042', 1045, and at the time of discriminating the existence of the held interruption, informs the discriminated result to the traveling OS. When there is no held interruption, the register 1042' discriminates whether an interruption having at least one real interruption priority order shared by the traveling OR and another OS is held by the control program or not, and when the interruption is held by the control program, informs the absence of a held interruption to be processed to the traveling OS.

53. 发明专利

JPH03241426A CACHE MEMORY SYSTEM 失效
公开(公告)号：JPH03241426A
公开(公告)日：1991-10-28
申请号：JP3927190
申请日：1990-02-20
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： MORIOKA MICHIO , KURITA KOZABURO , SAWAMOTO HIDEO , KOBAYASHI YOSHIKI , KOBAYASHI TAKAO
IPC分类号： G06F12/08 , G06F9/38
摘要： PURPOSE:To attain coincidence control between an instruction and data cache with the small amount of a hardware by detecting whether the data is stored in the other cache memory or not only when the data to be required to a cache memory is not present thereon, and making the data invalid when this data is present in the other cache memory. CONSTITUTION:A cache data identifying means 130 is provided to identify all information existing in an instruction and the data cache memory 152. When the data to be required to one cache is not present thereon, the required data is read out from a main memory 200 and newly registered and the cache data identifying means 130 detects whether the relevant data is present in another cache 122 or not. When this data is present in the other cache, this data is made to be invalid. Then, exclusive control is executed to inhibit the same data to be registered to the instruction cache 122 and the data cache 152. Thus, without providing an instruction change buffer, competition between instruction and data storage can be controlled in an instruction and data separating cache memory.

54. 发明专利

JPH0371247A BUFFER STORAGE CONTROLLER 失效
公开(公告)号：JPH0371247A
公开(公告)日：1991-03-27
申请号：JP20771689
申请日：1989-08-10
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO
IPC分类号： G06F12/08 , G06F12/10 , G11C5/06
摘要： PURPOSE:To ease the restriction of wiring by connecting m buffer address arrays each of which consists of n rows and allocating mXn comparators to all the mXn rows in all the buffer address arrays at the rate of 1 to 1. CONSTITUTION:Set of all rows 3-1 to 3-4, 3-1' to 3-4' of respective buffer address arrays(BAAs) are prepared independently of respective rows 2-13, 2-23 of an address translation buffer(TLB). Namely, a one BAA (n rows) is prepared for each row out of m rows of the TLB, so that mXn rows in total are secured in all the BAAs and each i-th row of the same has a same content. In such constitution, each one row RAM of the BAAs can be allocated to each of comparators 6-1 to 6-4, 7-1 to 7-4 at the rate of 1 to 1, so that respective rows of the TLB, the comparators corresponding to respectively rows and RAMs corresponding to respective rows of the BAAs can be divided into plural groups and each group can be independently arranged. Consequently, the mutual distance of targets to be connected is shortened, i.e. the wiring length is shortened, and the crossing of wirings can be removed.

55. 发明专利

JPH0253814B2 失效
公开(公告)号：JPH0253814B2
公开(公告)日：1990-11-19
申请号：JP7080284
申请日：1984-04-11
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO , ONODERA OSAMU
IPC分类号： G06F12/10
摘要： PURPOSE:To perform conversion into a real address of a real computer from a virtual address in the same processing time as that required for a bear machine, by using the same adder to perform simultaneously the addition of logical addresses of a virtual computer system and the addition of start addresses of a virtual resident computer system. CONSTITUTION:A logical address register 11 stores a virtual address, and this virtual address includes a segment index SX, a paging index PX and a byte index BX. The index SX, a segment table origin STO stored in a segment table origin register 12 and the contents alpha of a start address register 13 of a virtual resident computer are added simultaneously by a 3-input adder 31-1. Then qualification prefix conversion circuits 32-1-32-3 performs conversion successively to obtain a real address of a real computer corresponding to the virtual address stored in the register 11. This real address is stored to a real address register 22.

56. 发明专利

JPH02216532A SYSTEM FOR ADJUSTING PERFORMANCE OF COMPUTER 失效
公开(公告)号：JPH02216532A
公开(公告)日：1990-08-29
申请号：JP3627189
申请日：1989-02-17
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO , YAMAGATA MAKOTO , TAKEUCHI HIDENORI
IPC分类号： G06F9/22 , G06F9/30
摘要： PURPOSE:To objectively and easily adjust the relative performance of a low- order model with respect to a basic model by shifting control to a dummy time generation means after an instruction execution time which can be optionally set in a counter and which is previously decided has passed. CONSTITUTION:The instruction execution time measurement counter 1 measures the instruction execution time without waiting and stopping, and it generates a brake-in request when it counts a previously decided time TE. The brake-in request is treated in the same way as the other brake-in causes, and the break-in of the micro program in a specified routine is generated in the slit of an instruction. When break-in by the counter 1 occurs, control shifts to the dummy cycle routine of the micro program, and a previously decided time TD is consumed by permitting the routine to execute micro program-looping. Finally, the time TE is loaded in the counter 1. Thus, the relative performance of the low-order model with respect to the basic model can objectively and easily be adjusted.

57. 发明专利

JPH0262645A MEMORY PROTECTING SYSTEM 失效
公开(公告)号：JPH0262645A
公开(公告)日：1990-03-02
申请号：JP21585388
申请日：1988-08-29
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SAWAMOTO HIDEO , SHIOKAWA SHIZUO
IPC分类号： G06F12/14
摘要： PURPOSE:To attain the fine protection of memory by adding the data into the entry address data of a page table to instruct the memory protection for each one of blocks that divide a virtual space. CONSTITUTION:A segment index field 1a of a virtual address register 1 is used as an address to give an access to an address conversion buffer 2. The coincidence of page indexes is detected by a coincidence circuit 4, and a signal of the TLB bit is outputted. At the same time, a page protection bit P obtains an AND with a store request signal and the block protection bits B0-B7 obtain the AND with the signals obtained by decoding the higher 3 bits of a byte index field 1c via a decoder 3 and the store request signal through the AND gates 5 and 6 respectively. Then these bits secure the AND with the TLB bit signal via an OR gate 9 and then an AND gate 8. Thus a memory protection exception signal is produced.

58. 发明专利

JPH0212553A INPUT/OUTPUT EXECUTION SYSTEM FOR VIRTUAL COMPUTER 失效
公开(公告)号：JPH0212553A
公开(公告)日：1990-01-17
申请号：JP16475888
申请日：1988-06-30
申请人： HITACHI LTD
发明人： TANAKA TOSHIHARU , OTSUKI TORU , SATO HIROAKI , SAWAMOTO HIDEO , YAMAGATA MAKOTO , WATABE SHINYA , UMENO HIDENORI , HARAGUCHI MASATOSHI
IPC分类号： G06F13/10 , G06F9/318 , G06F9/455 , G06F9/46 , G06F9/48
摘要： PURPOSE:To efficiently execute the input/output instructions and the input/output interruption of a two VMs(virtual computers) with different architecture by executing the input/output instructions and the input/output interruption of the two VMs without interposing a control program(VMCP). CONSTITUTION:The computer is constituted of a main memory device 1000, a central processing unit 2000, an input/output processor 3000, an input/output controller 4000, and an input/output device 5000. And an OS in running is provided with first architecture for the input/output instruction of the first architecture issued by the OS, and when the input/output device 5000 to designate the input/output instruction is dedicated for the running OS, the input/output instruction is issued to the input/output device 5000, and when it is not dedicated for the running OS, it is indexed to the VMCP. In such a way, it is possible to execute the input/output instructions and the input/output interruption of the VMs with different architecture efficiently under a real computer.

59. 发明专利

JPS63259749A VIRTUAL STORAGE CONTROL SYSTEM 失效
公开(公告)号：JPS63259749A
公开(公告)日：1988-10-26
申请号：JP9301287
申请日：1987-04-17
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO , YAMAGATA MAKOTO
IPC分类号： G06F12/10 , G06F12/12
摘要： PURPOSE:To decrease UIC updating overheads by providing a means to store the frequency of a page-reference and the presence/absence of the rewriting of page-constant for every page of virtual space. CONSTITUTION:In an entry of a page table used for address conversion, R, C bits representing the page-reference frequency and the presence/absence of the rewriting of page content are provided. By designating the head and the length of the page table, the bit R can be read out even consecutively, and the need for obtaining a real page address by pursuing the chain of a page- frame-table PFT is eliminated, also, the need for using an RRB (Reset Reference Bit) instruction whose processing time is long for accessing a main storage key is made unnecessary even for referring to the RC bits, instead of it, an instruction for accessing general main storages can be used, hence the unreferring time interval counting UIC updating processing by an operating system OS can be made speedy. Also, even when the capacity of the main storage is increased, a memory for the bits R, C does not need to be added, therefore, the quantity of hardwares can be reduced.

60. 发明专利

JPS62174851A BUFFER DESCRIBING CONTROL SYSTEM 失效
公开(公告)号：JPS62174851A
公开(公告)日：1987-07-31
申请号：JP1564386
申请日：1986-01-29
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO , FUKUDA MASAHARU
IPC分类号： G06F12/08 , G06F12/14
摘要： PURPOSE:To check the address range of a request by having a mechanism that shows to which territory on the main storage (MS) the data of the block belongs corresponding to the block of a buffer storage (BS), and by assuming that the request has not hit the BS, when the request to the BS is not in the permitted territory. CONSTITUTION:When an output 12 is '0', namely, when it does not 'HIT' in the Fetch request, the request to an SCU for the block transmission is outputted, if necessary, and an absolute address 6 and request classification 7 are sent to the SCU. The SCU checks the address range of the request and reports to the buffer control part, when the request is outside the permitted range. Next, in the BS block cancel, a block-cancel address is stored in the address 6, and the information which shows whether the address is HR or not is sent from the SCU and stored in an address 7. Subsequent operation is performed similarly to the request from the command control part, the BAA 1 is accessed, and judging of a hit is executed.

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