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51. 发明专利

JPS62277754A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62277754A
公开(公告)日：1987-12-02
申请号：JP12145286
申请日：1986-05-27
申请人： HITACHI CHEMICAL CO LTD
发明人： TSUBOMATSU YOSHIAKI , FUKUTOMI NAOKI , IWASAKI YORIO , YASUOKA TAKUYA
IPC分类号： H01L23/50 , H01L21/60 , H01L23/12 , H01L23/498
摘要： PURPOSE:To spread a wiring region, to increase density further, to enable dealing-with and to remove the defective slip-off of a lead pin before pulling-up from solder by forming a hole reaching the head section of the lead pin from the surface side of an insulating layer formed on the head section side of the lead pin and being smaller than the head section of the lead pin and conducting the lead pin and the line of the surface of the insulating layer. CONSTITUTION:A hole is bored to a substrate 1 for a wiring board having insulating properties and the plating 2 of a through-hole is shaped, and a lead pin 3 is inserted. An insulating layer 4 is formed to a desired section on the inserting lead-pin head section side of the substrate 1. A metallic plate 6 is incorporated into the insulating layer, a hole is bored to a desired section, and the insulating layer is contact-bonded with a copper foil 5, thus also improving heat dissipation. A section as a via hole 7 in the copper foil 7 is removed through etching, the via hole reaching the head section of the lead pin and having a diameter smaller than the head section of the lead pin is shaped, using the copper foil 5 as a resist, the inside of the hole is conducted, a resist image is formed on the surface, and a desired conductor circuit pattern 8 is shaped. Lastly, a section on which an IC chip 9 is loaded is spot facing- worked up to the metal 6.

52. 发明专利

JPS6139598A Method of forming resist pattern 失效
标题翻译：形成电阻图案的方法
公开(公告)号：JPS6139598A
公开(公告)日：1986-02-25
申请号：JP15997584
申请日：1984-07-30
申请人： Hitachi Chemical Co Ltd
发明人： TSUBOMATSU YOSHIAKI , IWASAKI YORIO , KIDA AKINARI
IPC分类号： H05K3/06 , H05K3/00

53. 发明专利

JPS60263496A METHOD OF PRODUCING CIRCUIT BOARD 失效
公开(公告)号：JPS60263496A
公开(公告)日：1985-12-26
申请号：JP12020584
申请日：1984-06-12
申请人： HITACHI CHEMICAL CO LTD
发明人： KIDA AKINARI , FUKUTOMI NAOKI , IWASAKI YORIO , TSUBOMATSU YOSHIAKI , KAWASHIMA YUTAKA
IPC分类号： H05K3/26 , H05K3/20

54. 发明专利

JP2002237547A SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD, AND SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD 失效
公开(公告)号：JP2002237547A
公开(公告)日：2002-08-23
申请号：JP2001033172
申请日：2001-02-09
申请人： HITACHI CHEMICAL CO LTD
发明人： MORIIKE MICHIO , INOUE FUMIO , AWANO YASUHIKO , YAMAGUCHI REIKO , TSUBOMATSU YOSHIAKI
IPC分类号： H01L23/12 , H01L21/56
摘要： PROBLEM TO BE SOLVED: To provide a substrate suited for the small size and high density use and having superior reliability, by preventing a crack in package for a small semiconductor package and its manufacturing method, and to provide the semiconductor package and its manufacturing method. SOLUTION: The substrate is composed of at least a conductive pattern, connected to a semiconductor chip and an insulating base for supporting the conductive pattern. The substrate for the package has a stopping hole, which does not reach the side of the conductive pattern, on a face opposite to the conductive pattern and at the outer side of an area for mounting the semiconductor chip in the insulating base.

55. 发明专利

JP2002176124A BOARD FOR MOUNTING SEMICONDUCTOR, SEMICONDUCTOR PACKAGE USING THE BOARD, AND MANUFACTURING METHOD BOTH THEREOF 失效
公开(公告)号：JP2002176124A
公开(公告)日：2002-06-21
申请号：JP2000370865
申请日：2000-12-06
申请人： HITACHI CHEMICAL CO LTD
发明人： INOUE FUMIO , NAKAMURA HIDEHIRO , AWANO YASUHIKO , ENOMOTO TETSUYA , YAMAGUCHI REIKO , MORIIKE MICHIO , ENDO TOSHIHIRO , TSUBOMATSU YOSHIAKI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a low-cost semiconductor mounting board for reducing the diameter of a bent hole, along with a semiconductor package by using the semiconductor mounting board, and to provide the methods for manufacturing the semiconductor mounting board and the semiconductor package. SOLUTION: The semiconductor mounting board in the semiconductor package includes an insulating base, a connection terminal passing the insulating base, and a plurality of conductive patterns on at least one side of the insulating base. One or more conductive patterns are connected to the connection terminal, and the semiconductor mounting board has a hole, in which a space formed between the conductive pattern and a semiconductor-chip mounting insulating adhesive on the rear of the semiconductor chip up to the rear face thereof when a semiconductor chip is mounted on the conductive pattern is passed through to the rear face of the insulating base.

56. 发明专利

JP2002118203A SUBSTRATE FOR MOUNTING SEMICONDUCTOR, MANUFACTURING METHOD THEREFOR, SEMICONDUCTOR PACKAGE EMPLOYING THE SAME AND MANUFACTURING METHOD THEREFOR 失效
公开(公告)号：JP2002118203A
公开(公告)日：2002-04-19
申请号：JP2000311062
申请日：2000-10-11
申请人： HITACHI CHEMICAL CO LTD
发明人： YAMAGUCHI REIKO , INOUE FUMIO , AWANO YASUHIKO , TSUBOMATSU YOSHIAKI , IWASAKI YORIO , OHATA HIROTO
IPC分类号： H01L23/12 , H01L23/14
摘要： PROBLEM TO BE SOLVED: To provide a small semiconductor package which is excellent in miniaturization, densification, and also excellent in reliability by preventing the package from cracking and a substrate for mounting a semiconductor, and to provide an efficient method for manufacturing the substrate for mounting the semiconductor and a method for manufacturing the semiconductor package. SOLUTION: The substrate for mounting the semiconductor comprises a flexible insulating base material and a wiring conductor, and the base material has low moisture permeability. Thus, the efficient method for manufacturing the substrate for mounting the semiconductor and the method for manufacturing the semiconductor package can be obtained.

57. 发明专利

JP2002110858A SEMICONDUCTOR PACKAGE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2002110858A
公开(公告)日：2002-04-12
申请号：JP2001237791
申请日：2001-08-06
申请人： HITACHI CHEMICAL CO LTD
发明人： FUKUTOMI NAOKI , TSUBOMATSU YOSHIAKI , INOUE FUMIO , YAMAZAKI AKIO , OHATA HIROTO , HAGIWARA SHINSUKE , TAGUCHI NORIYUKI , NOMURA HIROSHI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor package substrate that can cope with the high integration of a semiconductor. SOLUTION: In an insulating support, a plurality of sets of wiring 2 are formed on one side, an LSI chip 3 is packaged in a polyimide film 20 where an opening is provided at a place where a soldering pole 7 that is an external connection terminal is formed in the wiring 2 for forming a through hole for the soldering pole 7 via a die-bonding tape 4' for allowing the LSI chip 3 to be continuous to the plurality of sets of wiring 2, the LSI chip 3 is sealed by resin 5, the soldering pole 7 that is continuous to the wiring 2 is formed in the through hole, and the polyimide film 20 is stamped out by a die for dividing into each package.

58. 发明专利

JP2001217351A CHIP SUPPORT BOARD FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE USING IT, AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2001217351A
公开(公告)日：2001-08-10
申请号：JP2000027173
申请日：2000-01-31
申请人： HITACHI CHEMICAL CO LTD
发明人： INOUE FUMIO , TSUBOMATSU YOSHIAKI , OHATA HIROTO , AWANO YASUHIKO , IWASAKI YORIO
IPC分类号： H01L23/14 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a chip support board for a semiconductor package, a semiconductor package using it, and its manufacturing method of less deflection, excellent in external connection reliability. SOLUTION: An insulating support board comprising at least three layers, namely a first layer, a second layer, and a third layer starting on the side where a metal wiring is formed, is provided. With thicknesses and thermal expansion factors of the layers as (T1, α1), (T2, α2), (T3, α3) in order, (T1/T2) as well as (T3/T2)

59. 发明专利

JP2000315746A CHIP SUPPORTING BOARD FOR SEMICONDUCTOR PACKAGE 失效
公开(公告)号：JP2000315746A
公开(公告)日：2000-11-14
申请号：JP2000115858
申请日：2000-04-12
申请人： SHARP KK , HITACHI CHEMICAL CO LTD
发明人： SODA YOSHIKI , MIYATA KOJI , INOUE FUMIO , YAMAZAKI AKIO , TSUBOMATSU YOSHIAKI , NAKAMURA HIDEHIRO , AWANO YASUHIKO , ICHIMURA SHIGEKI , YUSA MASAMI , IWASAKI YORIO
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To produce a highly reliable small semiconductor package by forming a hollow region communicating with a through hole between an insulating supporting board and an insulating film formed at a part for mounting a semiconductor chip thereby preventing package crack. SOLUTION: A die bond film 4 is bonded to the semiconductor mounting region of a supporting board. Since the die bond film 4 can sustain the state of flat film and an adhesive does not drip according to specified conditions, the die bond film 4 can be bonded only at a part close to the upper surface of a metal pattern part, e.g. wiring, without adhering to a bonding sheet 1 and an air gap, i.e., a hollow region 11, communicating with a through hole is formed between the bonding film 4 and the bonding sheet 1. Consequently, gas and steam being generated from the die bond film 4 during reflow can be discharged surely to the outside of a package and package crack can be prevented.

60. 发明专利

JP2000165018A MANUFACTURE FOR WIRING MEMBER 失效
公开(公告)号：JP2000165018A
公开(公告)日：2000-06-16
申请号：JP33210398
申请日：1998-11-24
申请人： HITACHI CHEMICAL CO LTD
发明人： NAKAMURA HIDEHIRO , TSUBOMATSU YOSHIAKI , ENOMOTO TETSUYA
IPC分类号： H05K1/11 , H01L23/12 , H05K3/06
摘要： PROBLEM TO BE SOLVED: To manufacture a wiring board to be used for an electric checking board for a contact conductivity by forming a wiring including through holes and metallic layer around the through holes by etching a metallic layer where resist image is not formed. SOLUTION: A board on which a metallic layer 1 is formed on an insulating material 2 of a laminated board is used. Next, a through hole 3 having a diameter of for example 0.1 mm is bored by using an NC drill machine. After that a resist film is laminated on a surface of a metallic layer of the substrate and a reflecting plate is placed on the resist film to expose from holes without resist. A resist image A is formed by development afterwards. After that, a resist image B is so formed on the rear side as holes at least to be closed. A copper layer is made half etching of 20-25 μm by liquid made of sulfuric acid and hydrogen peroxide. The resist is peeled by liquid of sodium hydroxide or potassium hydroxide. By the means bumps 7 having annular holes on the copper layer of 10 to 15 μm is formed.

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