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51. 发明专利

JPS55164951A OPERATION CONFIRMING SYSTEM FOR COMPUTER 失效
公开(公告)号：JPS55164951A
公开(公告)日：1980-12-23
申请号：JP7189679
申请日：1979-06-08
申请人： FUJITSU LTD
发明人： HAYASHI TATSUMI , OKAMOTO TETSUO , TAMURA HIROSHI
IPC分类号： G06F11/22
摘要： PURPOSE:To detect the defect of test circuit with a simple method, by providing the simulated circuit equivalent mechanically but different from the constitution, to the circuit to be tested used normally for computers to be tested and comparing the result of execution of test program respectively selected by both circuits. CONSTITUTION:The optimum processing circuits 4-1-4-n normally used for computers to be tested are provided with the processing circuit 40 without optimization (simulation circuit) having the processing function of the circuits 4-1-4-n mechanically, and the input information input via the input information line 11 is fed to the selection circuit 3 and the circuit 40. Further, the operation of the circuits 3 and 40 is switched with the signal of the mode control signal lines 13, 14 from the mode switch circuit 2. Further, when the circuit is operative, the circuits 4-1-4-n are selected to execute the test program processing corresponding to each function, and if the circuit 40 is operative, the test program processing is executed, the result of ?execution of both programs is compared at the selection circuit 5, and the result of comparison gives detection of the defect of the circuits 4-1-4-n.

52. 发明专利

JPS5178644A 失效
公开(公告)号：JPS5178644A
公开(公告)日：1976-07-08
申请号：JP79575
申请日：1974-12-29
申请人： FUJITSU LTD
发明人： OOKAWA MASAYUKI , TAMURA HIROSHI , YAMAMOTO KEISUKE , HIROWATARI SHOICHI
IPC分类号： G06F12/12 , G06F3/00 , G06F9/00 , G06F13/00

53. 发明专利

JPS5119453A PATSUFUA MEMORISEIGYOHOSHIKI 失效
公开(公告)号：JPS5119453A
公开(公告)日：1976-02-16
申请号：JP9107574
申请日：1974-08-08
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI , OOKAWA MASAYUKI , SHIMOMURA KEISUKE
IPC分类号： G06F12/12 , G06F12/08 , G06F13/00

54. 发明专利

JPS5111533A 失效
公开(公告)号：JPS5111533A
公开(公告)日：1976-01-29
申请号：JP8337274
申请日：1974-07-20
申请人： FUJITSU LTD
发明人： SHIMOMURA KEISUKE , OOKAWA MASAYUKI , TAMURA HIROSHI , HIROWATARI SHOICHI
IPC分类号： G11C13/04 , G06F12/12 , G06F12/16 , G06F13/00

55. 发明专利

JPS6240741B2 失效
公开(公告)号：JPS6240741B2
公开(公告)日：1987-08-29
申请号：JP3132782
申请日：1982-02-27
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16 , G06F15/16 , G06F15/177 , G06F17/16

56. 发明专利

JPS6155708B2 失效
公开(公告)号：JPS6155708B2
公开(公告)日：1986-11-28
申请号：JP13196380
申请日：1980-09-22
申请人： FUJITSU LTD
发明人： NAKATANI SHOJI , TAMURA HIROSHI
IPC分类号： G06F12/06 , G06F15/78 , G06F17/16

57. 发明专利

JPS6122830B2 JPS6122830B2 - 失效
公开(公告)号：JPS6122830B2
公开(公告)日：1986-06-03
申请号：JP17543180
申请日：1980-12-12
申请人： Fujitsu Ltd
发明人： TAMURA HIROSHI , NAKATANI SHOJI
IPC分类号： G06F17/16 , G06F9/38
CPC分类号： G06F9/3869

58. 发明专利

JPS6058503B2 失效
公开(公告)号：JPS6058503B2
公开(公告)日：1985-12-20
申请号：JP16616480
申请日：1980-11-26
申请人： FUJITSU LTD
发明人： UCHIDA KEIICHIRO , TAMURA HIROSHI , OKAMOTO TETSUO , OKUYA SHIGEAKI
IPC分类号： G06F9/38 , G06F17/16

59. 发明专利

JPS6057101B2 失效
公开(公告)号：JPS6057101B2
公开(公告)日：1985-12-13
申请号：JP10469580
申请日：1980-07-29
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI , NAKATANI SHOJI
IPC分类号： G06F12/06 , G06F12/02 , G06F17/16

60. 发明专利

JPS57113148A PRIORITY LEVEL CIRCUIT 失效
公开(公告)号：JPS57113148A
公开(公告)日：1982-07-14
申请号：JP18828280
申请日：1980-12-29
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI , NAKATANI SHIYOUJI , ITOU MIKIO , OINAGA YUUJI
IPC分类号： G06F9/48
摘要： PURPOSE:To obtain a circuit which exercises priority level control conforming to the operation of output equipment under simple control, by sending a signal, which prescribes timing determining priority, from an input signal source, and by determining the priority by this signal. CONSTITUTION:A priority level circuit receives priority levels from input signal sources and sends a signal to output equipment. For example, an information signal regarding the number of bytes, etc., of data is sent from a request input source to a 1/n specifying circuit, which sends a signal, corresponding to the number of bytes of the data, to a priority control circuit PTC. Then, the flip- flop circuit of the priority control circuit PTC outputs a control signal which prescribes timing determining a priority level to the priority level circuit PRT. Then, the priority level circuit PRT accepts said control signal, and priority level information, inputted through a request-signal register RQ, to determine the priority level.

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