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51. 发明专利

JPH0433138A CPU RUNAWAY MONITORING SYSTEM 失效
公开(公告)号：JPH0433138A
公开(公告)日：1992-02-04
申请号：JP14041290
申请日：1990-05-30
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , SHIRAI HIROAKI
IPC分类号： G06F11/30
摘要： PURPOSE:To restore CPU by itself by differentiating the output of a watchdog timer, inputting it to the reset terminal of runaway CPU, restarting CPU and clearing a runaway detection signal to a master device. CONSTITUTION:When the runaway of software occurs in CPU 21 on a slave-side, a timer 22 detects it and output is changed from H to L. A runaway signal transmission circuit 25 differentiates the output and generates the runaway detection signal of an L-level pulse in a prescribed width. The signal sets a read register 12 to L and CPU 11 recognizes that runaway occurs in CPU 21. On the other hand, the runaway detection signal is inputted to the reset terminal of CPU 21 and CPU 21 is reset and restarted.

52. 发明专利

JPH03227140A SYSTEM BUS CHANGEOVER SYSTEM 失效
公开(公告)号：JPH03227140A
公开(公告)日：1991-10-08
申请号：JP2144890
申请日：1990-01-31
申请人： FUJITSU LTD
发明人： SUZUKI SHOJI , SHIRAI HIROAKI
IPC分类号： H04B1/74
摘要： PURPOSE:To automatically execute active/standby changeover by always monitoring a fault of a duplicate bus tying a basic frame and an extension frame by means of software. CONSTITUTION:A basic frame 10 polls periodically status registers 25, 26 of an extension frame 20 and reads the content to monitor the system bus normally. As a result of monitoring, when a fault of an active system bus is found out and the bus changeover is set in the automatic mode, a bus selector 13 brings an H level of an ACT-N and an L level of an ACT-E being so far into L for the ACT-N and H for the ACT-E conversely. Thus, the ACT-N is sent in a path of 11-C1-21-23 and the ACT-E is sent in a path of 12-C2-22-24 to the extension frame 20 to select the buffer 23 to be inactive and the buffer 24 to be active. Thus, a bus fault is detected in terms of the software and the bus changeover is automated.

53. 发明专利

JPH02202738A SERIAL DATA RECEIVING CIRCUIT 失效
公开(公告)号：JPH02202738A
公开(公告)日：1990-08-10
申请号：JP2316489
申请日：1989-02-01
申请人： FUJITSU LTD
发明人： SUZUKI SHOJI , NAKAYAMA SHUNICHI , SHIRAI HIROAKI , NARA KOICHI
IPC分类号： H04L25/40 , H04L7/02 , H04L7/04
摘要： PURPOSE:To easily receive serial data even if a bit rate of the other party side is not known especially in a transmitting side and a receiving side by providing a clock generating part, a clock selecting part, a start bit detecting part, etc. CONSTITUTION:Plural clock groups obtained by bringing a reference clock to frequency division are always outputted from a clock generating part 1, and a clock selecting part 3 selects one clock in the clock group. On the other hand, a receiving bit inputted to a start bit detecting part 2 detects a prescribed start bit contained in receiving data, based on a clock outputted from the selecting part 3. While the detecting part 2 does not detect the start bit, the selecting part 3 selects successively from a higher clock or a lower clock in plural clocks, and when the start bit is detected, the output clock of the selecting part 3 is selected and fixed. In such a way, a data transfer part 4 transfers the receiving data by a clock of the time when the start bit is detected, therefore, even if each bit rate is not known in advance in the transmitting and receiving sides, the data can be transferred.

54. 发明专利

JPH01259644A CLOCK RECEPTION CIRCUIT 失效
公开(公告)号：JPH01259644A
公开(公告)日：1989-10-17
申请号：JP8761788
申请日：1988-04-08
申请人： FUJITSU LTD
发明人： SHIRAI HIROAKI , HASHIMOTO KENICHI , KIMURA SHUJI
IPC分类号： H04L1/22 , G06F1/04 , H04B1/74 , H04L7/00
摘要： PURPOSE:To prevent the hit of an intra-device clock at the time of the trouble of a reference clock by providing a first selection part to switch into the output of another clock reception at the time of the trouble generation of a currently used input clock or a preliminary input clock and a second selection part to switch into another PLL circuit at the time of the trouble generation of the currently used PLL circuit or the preliminary PLL circuit. CONSTITUTION:When one bit of an interruption is generated in the input clock, it is detected by one bit interruption detection circuits 212 and 222 in a clock reception part. The output of the second selection part is stopped for a prescribed period by adding a control signal to reference clock inhibit circuits 510 and 620. Consequently, the input clock can be smoothly received by a residual vibration in PLL circuits 510 and 520 from the interruption of the input clock after the release of the interruption.

55. 发明专利

JPH01171053A TERMINAL DEVICE CONTROL SYSTEM 失效
公开(公告)号：JPH01171053A
公开(公告)日：1989-07-06
申请号：JP33518087
申请日：1987-12-25
申请人： FUJITSU LTD
发明人： SUZUKI SHOJI , NARA KOICHI , SHIRAI HIROAKI , MARUYAMA AKIRA
IPC分类号： G06F13/12
摘要： PURPOSE:To flexibly correspond to various system constitutions by recognizing a terminal device to connect a system control part and giving the control information necessary to the control of the terminal device to a terminal control part. CONSTITUTION:A system control part 101 identifies a terminal part 103 by the identification information read from an identification information recording means 121 and a control information retrieving means 111 retrieves a control information accumulating means 112 and necessary control information is obtained. Based on the control information, the writing and necessary processing of data to a control information storing part 122 of a terminal control part 102 are executed and the control of the terminal control part 102 and the terminal part 103 is executed. Thus, the correspondence to various system constitutions can be executed and the alteration of the control program and data table can be facilitated.

56. 发明专利

JPS631229A POWER SUPPLY HOLDING SYSTEM FOR ELECTRICAL EQUIPMENT 失效
公开(公告)号：JPS631229A
公开(公告)日：1988-01-06
申请号：JP14291786
申请日：1986-06-20
申请人： FUJITSU LTD
发明人： SHIRAI HIROAKI , OGURA TAKAYUKI , IYOTA TOSHIO , HASHIMOTO KENICHI
IPC分类号： G05F1/10 , H04L13/00 , H04L29/00
摘要： PURPOSE:To prevent a case where an electrical equipment is kept under an abnormal state in a break mode of a power supply by connecting two power switches in parallel between the electrical equipmemt and the power supply, breaking the 2nd power switch when a prescribed time passed after the 1st power switch is broken and meanwhile applying the processing required for break of the power supply. CONSTITUTION:The 1st and 2nd power switches SW1 and SW2 are connected in parallel between a power supply 1 of AC100V and an A/D converter 2. When the SW1 is turned off, the signal 1 of a contact S3 is set at an H level. This signal 1 is used as the trigger TRG input of a timer 4 as well as the selection signal of a selector SEL6. The timer 4 counts the processing time required for break of the power supply 1 and the output of the timer 4 is changed to an H level from an L level after a prescribed time. Thus a relay RL5 turns off the relay contacts rl1 and rl2 of the SW2. While the SEL6 that transmitted the primary signal 5 to an exchange station 8 before the SW1 is turned off selectes the power supply break signal 4 and sends it to the station 8 in response to the signal 1 set at an H level at the contact S3.

57. 发明专利

JPS6217903B2 失效
公开(公告)号：JPS6217903B2
公开(公告)日：1987-04-20
申请号：JP2143480
申请日：1980-02-22
申请人： FUJITSU LTD
发明人： YAMADA JUSAKU , NONAKA KENJI , TAKEDA KYOSHI , SHIRAI HIROAKI
IPC分类号： H04B1/04 , H04B10/00 , H04B10/07 , H04B10/556 , H04L29/00

58. 发明专利

JPS6282840A BUS TERMINATION SYSTEM 失效
公开(公告)号：JPS6282840A
公开(公告)日：1987-04-16
申请号：JP22401785
申请日：1985-10-08
申请人： FUJITSU LTD
发明人： SHIRAI HIROAKI , OGURA TAKAYUKI , IYOTA TOSHIO , HASHIMOTO KENICHI
IPC分类号： G06F3/00
摘要： PURPOSE:To omit a receiving unit provided with termination parts, to use only one kind of receiving units and to release the restriction of packaging positions by extending the final end of a bus up to a transmitting unit to terminate the bus by the transmitting unit. CONSTITUTION:When a digital signal is to be transmitted from a transmitting unit 1-1 to plural receiving units through a bus 7 for terminating a termination parts 8 on the final end, the final end of the bus 7 is taken in the unit 1-1. Namely, the parts 8 is inserted into the unit 1-1 and terminated in the unit 1-1. In said procedure, restriction to package a receiving unit with a terminating parts on the final end position of the bus 7 without fail in the initial stage at the packaging of the receiving unit can be omitted. Since the receiving unit with the terminating parts can be omitted, only one kind of receiving units may be used and the restriction of packaging positions can be released.

59. 发明专利

JPS60160220A DRIFT DETECTING CIRCUIT 失效
公开(公告)号：JPS60160220A
公开(公告)日：1985-08-21
申请号：JP1563684
申请日：1984-01-31
申请人： FUJITSU LTD
发明人： IYOTA TOSHIO , OGURA TAKAYUKI , HASHIMOTO KENICHI , SHIRAI HIROAKI
IPC分类号： H03L7/095
摘要： PURPOSE:To improve the accuracy and to attain unequivocal adjustment after the frequency is decided by using a TTL level in place of the method comparing an analog threshold value and a DC voltage to detect digitally a drift. CONSTITUTION:An input frequency enters a monostable multivibrator 9 from a terminal a and the monostable multivibrator 9 generates a pulse functioning as a threshold value detecting the drift at the leading edge of the input frequency. Moreover, an output frequency of a frequency divider 6 enters a monostable multivibtrator 8, which generates a pulse functioning as a threshold value to detect the drift at the leading edge. When the input frequency and the output frequency of the frequency divider 6 is in phase and there is no phase difference, the level of a terminal Q of a D flip-flop 10 remains ''0''. When the oscillating frequency of a voltage controlled oscillator 4 is shifted and there is a phase difference between the input frequency and the output frequency of the frequency divider 6, the level of the terminal q of the D flip-flop 10 or 11 goes to ''1'', an AND circuit 14 is turned on via an OR circuit 12 and a drift warning is transmitted from a terminal C.

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