专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

JP2014057077A Stacked semiconductor devices including master device 审中-公开
标题翻译：堆叠式半导体器件，包括主器件
公开(公告)号：JP2014057077A
公开(公告)日：2014-03-27
申请号：JP2013214655
申请日：2013-10-15
申请人： Conversant Intellectual Property Management Inc , コンバーサント・インテレクチュアル・プロパティ・マネジメント・インコーポレイテッドConversant Intellectual Property Management Inc.
发明人： KIM JIN-KI
IPC分类号： H01L27/10 , G11C5/00 , G11C16/02 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C5/063 , G11C5/02 , G11C5/06 , G11C16/30 , H01L21/50 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/05573 , H01L2224/13025 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a system comprising a stack.SOLUTION: The stack includes: a first non-volatile memory chip; and a second non-volatile memory chip lacking in at least some non-core circuits; and a plurality of electrical paths extending between the first non-volatile memory chip and the second non-volatile memory chip. The electrical paths make it easier for the first non-volatile memory chip to provide the second non-volatile memory chip with signals and voltages needed for device operations.
摘要翻译：要解决的问题：提供包括堆栈的系统。解决方案：堆栈包括：第一非易失性存储器芯片; 以及在至少一些非核心电路中缺少的第二非易失性存储器芯片; 以及在第一非易失性存储器芯片和第二非易失性存储器芯片之间延伸的多个电气路径。电路使得第一非易失性存储器芯片更容易为第二非易失性存储器芯片提供器件操作所需的信号和电压。

42. 发明专利

JP2014053055A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014053055A
公开(公告)日：2014-03-20
申请号：JP2012196392
申请日：2012-09-06
申请人： Toshiba Corp , 株式会社東芝
发明人： KOYANAGI MASARU
IPC分类号： G11C5/00 , G11C16/02 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , G06F3/0688 , G11C5/063 , G11C8/12 , G11C16/0483 , G11C16/08 , G11C29/88 , H01L23/481 , H01L23/50 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/13091 , H01L2924/1438 , H03K99/00 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of selecting a plurality of laminated chips.SOLUTION: A plurality of chips 6-1 to 6-4 respectively include at least first and second through vias V-4, V-5 that transmit at least first and second address signals, and are electrically connected to each other and stacked on one another through the first and second through vias. First selective circuits 15, 16 are provided for the respective chips, include a logic circuit for selecting a chip on the basis of at least the first and second address signals, and supply to a next stage chip the result obtained by calculating the first and second address signals.
摘要翻译：要解决的问题：提供能够选择多个层叠芯片的半导体器件。解决方案：多个芯片6-1至6-4分别包括至少第一和第二通孔V-4，V-5，其传输至少第一和第二地址信号，并且彼此电连接并且通过第一和第二通孔彼此堆叠。为各芯片提供第一选择电路15,16，包括至少基于第一和第二地址信号来选择芯片的逻辑电路，并向下一级芯片提供通过计算第一和第二地址信号获得的结果地址信号

43. 发明专利

JP5448697B2 Semiconductor memory device and data processing system 有权
公开(公告)号：JP5448697B2
公开(公告)日：2014-03-19
申请号：JP2009235480
申请日：2009-10-09
申请人：ピーエスフォールクスコエスエイアールエルPS4 Luxco S.a.r.l.
发明人：誉佐藤 , 淳一林
IPC分类号： G11C11/406 , G06F12/00 , G11C5/00 , H01L21/8242 , H01L27/00 , H01L27/10 , H01L27/108
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/4072 , G11C11/4076 , G11C16/20 , G11C2211/4061
摘要： To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation.

44. 发明专利

JP2013542529A Data signal mirroring 有权
公开(公告)号：JP2013542529A
公开(公告)日：2013-11-21
申请号：JP2013536601
申请日：2011-10-24
申请人：マイクロンテクノロジー, インク.
发明人：エム．アブラハム，マイケル , エス．フィーリー，ピーター
IPC分类号： G06F13/16 , G11C5/00
CPC分类号： G06F17/30575 , G06F13/1694 , G11C7/1006
摘要： Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data inputs/outputs of a memory component, and responsive to determining that a mirrored version of the particular data pattern is received by the memory component, configuring the number of data inputs/outputs to be mirrored.

45. 发明专利

JP5290516B2 Memory devices, system having a memory device, and method of operation implantable device 有权
公开(公告)号：JP5290516B2
公开(公告)日：2013-09-18
申请号：JP2006521766
申请日：2004-05-12
申请人：サンディスクアイエルリミテッド
发明人：アブラハム、メイル , インバル、ダン , パズ、ズィブ
IPC分类号： G11C7/00 , G06F20060101 , G06F12/00 , G06F12/06 , G06F13/28 , G11C5/00 , G11C11/401 , G11C14/00 , G11C16/02
CPC分类号： G11C14/00 , G06F9/4403 , G06F9/4406 , G06F9/44573 , G11C14/0018
摘要： A memory device includes two dies. A first memory is fabricated on one die. A controller of the first memory is fabricated on the other die. Also fabricated on the other die is another component, such as a second memory, that communicates with a host system using a plurality of signals different from the signals used by the first memory. The device includes a single interface for communicating with the host system using only the respective signals of the second component. In a most preferred embodiment, the first memory is a NAND flash memory and the second memory is a SDRAM.

46. 发明专利

JP2013168169A Memory device, system with memory device, and operation method of embedded type device 有权
标题翻译：存储器件，具有存储器件的系统以及嵌入式器件的操作方法
公开(公告)号：JP2013168169A
公开(公告)日：2013-08-29
申请号：JP2013084237
申请日：2013-04-12
申请人： Sandisk Il Ltd , サンディスクアイエルリミテッド
发明人： MEIR AVRAHAM , DAN INBAR , ZIV PAZ
IPC分类号： G06F12/06 , G06F20060101 , G06F12/00 , G06F13/28 , G11C5/00 , G11C14/00 , G11C16/02 , G11C16/04
CPC分类号： G11C14/00 , G06F9/4403 , G06F9/4406 , G06F9/44573 , G11C14/0018
摘要： PROBLEM TO BE SOLVED: To provide a memory device capable of communicating with a host system via a single external bus, and comprising both a NAND flash memory and an SDRAM.SOLUTION: A memory device comprises two dies. A first memory is fabricated on one die. A controller of the first memory is fabricated on the other die. Also another component, such as a second memory that communicates with a host system by using a plurality of signals different from signals used by the first memory is fabricated on the other die. The device comprises a single interface for communicating with the host system by using only signals of a second component. In a most preferred embodiment, the first memory is a NAND flash memory and the second memory is an SDRAM.
摘要翻译：要解决的问题：提供能够经由单个外部总线与主机系统通信并且包括NAND闪存和SDRAM两者的存储器件。解决方案：存储器件包括两个管芯。第一个存储器在一个管芯上制造。第一存储器的控制器在另一个芯片上制造。还有另一个部件，例如通过使用与第一存储器使用的信号不同的多个信号与主机系统通信的第二存储器。该设备包括用于仅使用第二组件的信号与主机系统通信的单个接口。在最优选的实施例中，第一存储器是NAND闪速存储器，第二存储器是SDRAM。

47. 发明专利

JP2013157058A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013157058A
公开(公告)日：2013-08-15
申请号：JP2012017512
申请日：2012-01-31
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： HAYASHI JUNICHI
IPC分类号： G11C29/00 , G11C5/00 , G11C11/401 , H01L21/8242 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/10 , H01L27/108
CPC分类号： H01L2224/16145 , H01L2224/16225 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To relieve defects in the unit of memory bank without providing a redundant bank in a core chip and without newly providing a current path corresponding to a redundant bank.SOLUTION: A semiconductor device includes a core chip CC0 including memory banks B0-B7, and an interface chip IF placed on the core chip CC0 and serving as an interface between the core chip CC0 and outside, with the interface chip IF having a redundant bank RB0 configured to be replaceable with one defective memory bank of the memory banks B0-B7 of the core chip CC0.
摘要翻译：要解决的问题：为了减轻存储体单元中的缺陷，而不需要在核心芯片中提供冗余库，而不需要重新提供与冗余库相对应的电流路径。解决方案：一种半导体器件包括一个包括存储体B0 -B7，以及放置在核心芯片CC0上并用作核心芯片CC0和外部之间的接口的接口芯片IF，其中接口芯片IF具有冗余组RB0，其被配置为可与存储体的一个缺陷存储体组替换核心芯片CC0的B0-B7。

49. 发明专利

JP2013089001A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013089001A
公开(公告)日：2013-05-13
申请号：JP2011228532
申请日：2011-10-18
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： RIHO YOSHIRO
IPC分类号： G06F12/00 , G11C5/00
CPC分类号： G11C11/4063 , G11C5/063 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/40 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C29/023 , G11C29/028 , H01L25/0657 , H01L2224/16145 , H01L2924/1305 , H01L2924/13091 , H03L7/0812 , H03L7/097 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To allow the phase of a data signal transmitted to an input circuit of a control chip from an output circuit of a controlled chip to coincide with the phase of a synchronous signal supplied to the input circuit.SOLUTION: A semiconductor device comprises a first controlled chip 110 and a control chip 120 laminated with it. The first controlled chip includes a first circuit 117 that outputs a data signal in response to a synchronous signal, an input/output circuit 118 that synchronizes the data signal with a delayed synchronous signal and output it to a data terminal, and a replica circuit 119 that is a circuit imitating an output circuit and that outputs a replica signal to a first replica terminal in synchronization with the delayed synchronous signal. The control chip includes a first control circuit 126 that outputs the synchronous signal and receives the data signal, a delay adjustment circuit 130 that delays the synchronous signal and outputs it as a delayed synchronous signal, a phase comparison circuit 128 that compares the phase of the replica signal with the phase of the synchronous signal, and a delay control circuit 129 that controls the delay amount of the delay adjustment circuit on the basis of the comparison result of the phase comparison circuit.
摘要翻译：要解决的问题：允许从受控芯片的输出电路发送到控制芯片的输入电路的数据信号的相位与提供给输入电路的同步信号的相位一致。解决方案：半导体器件包括第一受控芯片110和与其层叠的控制芯片120。第一受控芯片包括响应于同步信号输出数据信号的第一电路117，使数据信号与延迟的同步信号同步并将其输出到数据端的输入/输出电路118和复制电路119 这是模拟输出电路的电路，并且与延迟的同步信号同步地将复制信号输出到第一副本终端。控制芯片包括输出同步信号并接收数据信号的第一控制电路126，延迟同步信号并将其作为延迟同步信号输出的延迟调整电路130;相位比较电路128，具有同步信号的相位的复制信号，以及基于相位比较电路的比较结果来控制延迟调整电路的延迟量的延迟控制电路129。版权所有（C）2013，JPO＆INPIT

50. 发明专利

JP5161667B2 Semiconductor device, a semiconductor system 有权
公开(公告)号：JP5161667B2
公开(公告)日：2013-03-13
申请号：JP2008163260
申请日：2008-06-23
申请人：スパンションエルエルシー
发明人：健太加藤
IPC分类号： G11C11/41 , G11C5/00 , G11C11/401 , G11C11/413 , H01L27/10

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式