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41. 发明专利

JPH01194513A DYNAMIC TYPE FREQUENCY DIVIDER 失效
公开(公告)号：JPH01194513A
公开(公告)日：1989-08-04
申请号：JP27001188
申请日：1988-10-25
申请人： NEC CORP
发明人： TAKAHASHI MASARU
IPC分类号： H03K23/54 , H03K23/52
摘要： PURPOSE:To easily cause a dividable frequency to be variable and to decrease a dividable lower limit frequency by using variable capacity or fixed capacity. CONSTITUTION:By attaching variable capacity diodes DI1 and DI2 to the output of transfer gates 3 and 5 in a dynamic type divider 1 and causing the capacity to be variable, the holding time of a charge is changed and the dividable frequency is made variable. Since the joining capacity of the variable capacity diodes DI1 and DI2 is made variable by a voltage, a voltage for capacity variability is added from an external part. When fixed capacity C3 and C4 are provided instead of the variable capacity diodes DI1 and DI2, a lower limit operating frequency can be decreased. Thus, by incorporating the variable capacity or fixed capacity, the dividable frequency can be easily made variable from the external part of an integrated circuit or the dividable lower limit frequency can be decreased.

42. 发明专利

JPS6477223A FREQUENCY DIVIDING CIRCUIT 失效
公开(公告)号：JPS6477223A
公开(公告)日：1989-03-23
申请号：JP23256087
申请日：1987-09-18
申请人： HITACHI LTD
发明人： HAYASHI YOSHIHIKO , OSAKI AKIO
IPC分类号： H03K23/54 , H03K23/64
摘要： PURPOSE:To extend an operating frequency range and a variable range by controlling a prescaler only in one frequency division cycle by a terminal count signal of a preset counter in a frequency dividing circuit consisting of the prescaler consisting of plural D FFs and the preset counter. CONSTITUTION:Normally, a prescaler 100 supplies an N-divided clock to a preset counter (PSC) 11. The PSC 11 counts the N-divided clock, and the PSC 11 sends a terminal count signal TC to the prescaler 100 when terminating prescribed counting. The prescaler 100 divides the frequency by one of preliminarily set N-2N-1 in on frequency division cycle after reception of the signal TC. Then, the PSC 11 divides the frequency of the N-divided clock by K (>=0), and thereafter, the prescaler divides the frequency by J (N

43. 发明专利

JPS6462021A VARIABLE FREQUENCY DIVIDER CIRCUIT 失效
公开(公告)号：JPS6462021A
公开(公告)日：1989-03-08
申请号：JP21936287
申请日：1987-09-02
申请人： FUJITSU LTD
发明人： SHINOHARA SHIGERU , NAKAHARA HIDETOSHI
IPC分类号： H03K23/64 , H03K23/54 , H03K23/66
摘要： PURPOSE:To obtain a variable frequency divider circuit not incurring much trouble by receiving a value A set by an m-bit binary number and varying the frequency divider ratio while varying the setting value A. CONSTITUTION:Number of output terminals of a decoder 1 receiving the value A set in m-bit binary number, let (m) be 3 and the setting value A be 2, is 8, the loworder two-terminal of the 8 sets of output terminals goes to a level 1 through a bit width setting means 2 and the signals whose level is at logical 1 at the two terminals are given to parallel signal input terminals So of an 8-bit shift register 3. The series signal output terminal So is connected to the serial signal input terminal Si to form a ring counter, then signals two of which among 8 series signals are at logical 1 are outputted repetitively and given to the input terminal of a 1/N frequency divider 4 to enable the divider at 1-level input. Thus, an output whose frequency divider ratio is (2 .N)/A=(8.N)/2 is obtained from the 1/N frequency divider 4. Thus, the variable frequency divider circuit incurring much trouble is obtained.

44. 发明专利

JPS6316926B2 失效
公开(公告)号：JPS6316926B2
公开(公告)日：1988-04-12
申请号：JP4014979
申请日：1979-04-03
申请人： SEIKO EPSON CORP
发明人： MOROZUMI SHINJI
IPC分类号： G04G3/02 , G04C3/00 , H03K5/13 , H03K5/133 , H03K5/134 , H03K23/52 , H03K23/54 , H03K23/66

45. 发明专利

JPS639411B2 失效
公开(公告)号：JPS639411B2
公开(公告)日：1988-02-29
申请号：JP9690678
申请日：1978-08-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAMADA KUNIHIRO
IPC分类号： H03K23/44 , H03K23/54

46. 发明专利

JPS62202617A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS62202617A
公开(公告)日：1987-09-07
申请号：JP4422886
申请日：1986-03-03
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： FUJITA SHUICHI , MIZUTANI TAKASHI , YANAGAWA FUMIHIKO
IPC分类号： H03K23/54 , H01L29/80 , H03K23/52
摘要： PURPOSE:To realize an ultrahigh speed frequency divider with low power consumption by using an inverter obtaining inverting and noninverting outputs at the same time and increasing a small signal gain so as to use two inverters in a loop at minimum. CONSTITUTION:Inverting and noninverting outputs are obtained at the same time in a semiconductor integrated circuit capable of attaining the ultrahigh speed frequency operation and SCFL constitution inverters I1, I2 having a large small-signal gain and large operating margin are used. In repeating the input signal change, a signal of period 2T having a double period T of external input terminals X1, X2 appears at an external output terminal Y1=(B12) and a frequency being a half of that of the input signal is outputted. In this case, before the change in the output B12 of the inverter I2 is confirmed, a transmitting gate T3 of the next stage is conductive and erroneous information is sent to the inverter I1 of the next stage. Then the error above is prevented by satisfying the relation of the input period T and the propagation delay time tpd of the inverter to be tpd

47. 发明专利

JPS6212699B2 失效
公开(公告)号：JPS6212699B2
公开(公告)日：1987-03-20
申请号：JP4653778
申请日：1978-04-21
申请人： HITACHI LTD
发明人： TAMYA MASAO , YAMASHIRO OSAMU
IPC分类号： H03K23/52 , H03K3/3568 , H03K23/54

48. 发明专利

JPS6226920A TIMING GENERATOR 失效
公开(公告)号：JPS6226920A
公开(公告)日：1987-02-04
申请号：JP16569485
申请日：1985-07-29
申请人： CANON KK
发明人： SENDA MAKOTO , MORISHITA AKIRA , NAKAMURA YASUO
IPC分类号： H03K5/15 , H03K5/156 , H03K23/54
摘要： PURPOSE:To obtain a timing generator excellent in extending performance and general-purpose applications such as ease of timing design and ease of external setting change of timing period by using a selection circuit to select a delay circuit externally, thereby obtaining plural periods of timings. CONSTITUTION:A ring counter 100 having a stage number (delay circuit number) corresponding to the maximum period among desired timing periods consists of a selection circuit 103 selecting any of stage outputs by an external command to input the result to the 1st stage of the ring counter, and a OR circuit 101 receiving plural outputs of delay circuits corresponding to the pulse change point and an inverse delay circuit 102. As the input of the OR circuit 101, the output of the stage corresponding to the position of the desired timing change (0 to 1 or 1 to 0) is selected as the input and the inverse delay circuit 102 changes the logic state only with logical 1 level of logical sum. Thus, the timing period is decided according to the number of stage and the pulse change is decided by the position of the delay circuit. Moreover, the period is changed optionally by the selection circuit 103 up to the total number of the delay circuits externally.

49. 发明专利

JPS61295720A TEST CIRCUIT 失效
公开(公告)号：JPS61295720A
公开(公告)日：1986-12-26
申请号：JP13961485
申请日：1985-06-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： HONGO KATSUNOBU , SHICHINOHE DAISUKE
IPC分类号： H03K19/00 , H03K5/15 , H03K21/00 , H03K21/40 , H03K23/54
摘要： PURPOSE:To test external circuits, one by one, individually by connecting a changeover gate to shift registers which constitute a shift counter, and selecting the output of an exclusive OR gate for feedback when no test is taken and an input from an external input terminal when a test is taken. CONSTITUTION:A changeover control signal Test is held at 'L' in normal operation (when no test is taken) and the output of the exclusive OR gate 16 is selected by the changeover gate 3. When a test is taken, the changeover control signal Test is held at 'H' and data inputted from a setting data input terminal 4 for the test is selected by the changeover gate 3. In this state, set data of flip-flops 11-15 are inputted from the set data input terminal 4 in synchronism with a clock phi to set outputs Q1-Q5. Here, when the combination of the outputs Q1-Q5 is so set that a decoding output T1 is 'H', the decoding output T1 goes up to 'H' and an external circuit controlled with the decoding output T1 operates. Thus, decoding outputs T1-T4 are made to go up to 'H' in order.

50. 实用新型

JPS6145654Y2 失效
公开(公告)号：JPS6145654Y2
公开(公告)日：1986-12-22
申请号：JP18204383
申请日：1983-11-24
IPC分类号： H03J3/18 , H03J5/00 , H03K23/54 , H03K23/64

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