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41. 发明专利

JP2005166929A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005166929A
公开(公告)日：2005-06-23
申请号：JP2003403283
申请日：2003-12-02
申请人： Toshiba Corp , 株式会社東芝
发明人： SEKINE KATSUYUKI , TSUNASHIMA YOSHITAKA , INUMIYA SEIJI , KANEKO AKIO , SATO MOTOYUKI , EGUCHI KAZUHIRO
IPC分类号： H01L21/316 , H01L21/314 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31645 , H01L29/518
摘要： PROBLEM TO BE SOLVED: To provide a method for forming an insulating film with a reliability.
SOLUTION: A silicate film 12 containing a metal (e.g., hafnium) is formed on a silicon substrate 10. Subsequently, the silicon substrate 10 is subjected to a heat treatment in an ND
3 gas atmosphere, whereby nitrogen (N) and heavy hydrogen (D) are introduced into a silicate film 12. Heavy hydrogen (D) is introduced into the silicate film 12 in place of hydrogen (H), whereby a reliability of the silicate film 12 is enhanced.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可靠性形成绝缘膜的方法。解决方案：在硅衬底10上形成含有金属（例如铪）的硅酸盐膜12。随后，在氮气气氛中对硅衬底10进行热处理，由此将氮（N）和重氢（D）引入硅酸盐膜12中。将重氢（D）引入硅酸盐膜12中以代替氢（H），从而提高硅酸盐膜12的可靠性。版权所有（C）2005，JPO＆NCIPI

42. 发明专利

JP2005158998A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2005158998A
公开(公告)日：2005-06-16
申请号：JP2003395307
申请日：2003-11-26
申请人： Toshiba Corp , 株式会社東芝
发明人： INUMIYA SEIJI , KANEKO AKIO , SATO MOTOYUKI , SEKINE KATSUYUKI , EGUCHI KAZUHIRO , TSUNASHIMA YOSHITAKA
IPC分类号： H01L29/423 , H01L21/316 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/6656 , H01L21/28202 , H01L21/823828 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for realizing a high performance semiconductor device with low power consumption by restraining an abnormal shift of flat band voltage in a MOS transistor, which employs a high dielectric insulating film such as a hafnium silicate film as a gate insulating film and a polycrystalline silicon (or silicon and germanium) film as a gate electrode.
SOLUTION: A silicon film or the like which serves as at least a part of a gate electrode 4 is formed on the gate insulating film 3, and thereafter a nitriding layer 5 or an oxidation layer is formed on an electrode/insulating film interface by annealing the silicon film or the like in a nitriding atmosphere like NO gas and NH
3 gas or in an oxidizing atmosphere like O
2 gas. Further, a silicon film which serves as at least a part of the gate electrode is formed on the gate insulating film, into which any of oxygen, fluorine, and carbon is in turn introduced. A resultant sample is annealed to form any of a nitriding layer, an oxidation layer, a fluorinating layer, and a carbonizing layer on a gate electrode/gate insulating film interface.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种通过抑制MOS晶体管中的平坦带电压的异常移位来实现低功耗的高性能半导体器件的制造方法，MOS晶体管采用高介电绝缘膜，例如硅酸铪作为栅极绝缘膜的膜和作为栅电极的多晶硅（或硅和锗）膜。解决方案：在栅极绝缘膜3上形成用作至少一部分栅电极4的硅膜等，然后在电极/绝缘膜上形成氮化层5或氧化层通过在诸如NO气体和NH 3 SB气体的氮化气氛中或在诸如O 2 SB气体的氧化气氛中退火硅膜等。此外，在栅绝缘膜上形成用作至少一部分栅电极的硅膜，其中导入氧，氟和碳中的任一个。将所得样品退火以在栅极/栅极绝缘膜界面上形成氮化层，氧化层，氟化层和碳化层中的任一种。版权所有（C）2005，JPO＆NCIPI

43. 发明专利

JP2005108875A Semiconductor device and its fabricating process 有权
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2005108875A
公开(公告)日：2005-04-21
申请号：JP2003335966
申请日：2003-09-26
申请人： Toshiba Corp , 株式会社東芝
发明人： KANEKO AKIO , SEKINE KATSUYUKI , SATO MOTOYUKI , INUMIYA SEIJI , EGUCHI KAZUHIRO
IPC分类号： H01L21/283 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8238 , H01L23/48 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/823842 , H01L21/823857 , H01L29/495 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a good semiconductor device employing one kind of metal in gate electrode of an nMOS and a pMOS, and to provide its fabricating process. SOLUTION: The semiconductor device comprises a semiconductor substrate (101), a gate insulation film (105) composed of a material principally comprising a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO 2 , or a mixture of a tetravalent metal oxide and SiON, a gate electrode (115) composed of a metal having a work function of 4-5.5 eV. The gate insulation film contains B when an nMOS structure is formed on the semiconductor substrate, and contains at least one of P and As when a pMOS structure is formed on the semiconductor substrate. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供在nMOS和pMOS的栅电极中采用一种金属的良好半导体器件，并提供其制造工艺。解决方案：半导体器件包括半导体衬底（101），由主要包含四价金属氧化物的材料组成的栅绝缘膜（105），四价金属氧化物和SiO 2 SB的混合物 >或四价金属氧化物和SiON的混合物，由功函数为4-5.5eV的金属构成的栅电极（115）。当在半导体衬底上形成nMOS结构时，栅绝缘膜含有B，并且当在半导体衬底上形成pMOS结构时，包含P和As中的至少一种。版权所有（C）2005，JPO＆NCIPI

44. 发明专利

JP2004281494A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2004281494A
公开(公告)日：2004-10-07
申请号：JP2003067621
申请日：2003-03-13
申请人： Toshiba Corp , 株式会社東芝
发明人： INUMIYA SEIJI , EGUCHI KAZUHIRO
IPC分类号： C23C16/42 , H01L21/28 , H01L21/318 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28202 , H01L21/2807 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To form a structure in which an oxide film or an oxynitride film is provided between the surface of a silicon semiconductor substrate and an oxynitride film which are high dielectric constant materials containing metal and silicone so that the suppression of an increase of the interface level density and the suppression of generation of fixed electric charges can be compatible. SOLUTION: To suppress unwanted nitriding of a silicon semiconductor substrate, it is effective to form a silicon oxide film or an oxynitride film of 1 nm or less on the interface between a high dielectric constant material film and the silicon substrate. However, electric charges are generated on the interface between the interface layer and the high dielectric constant material film and improvement of the mobility cannot be realized due to the electric charges. A film 2 of a high dielectric constant material containing a metal element and a silicone element is deposited on the surface of the silicon semiconductor substrate 1, and then interface oxidation 3 is conducted from above the high dielectric constant material, and the film of a high dielectric constant material is subjected to nitriding 4. By interface oxidation from above the film of a high dielectric constant material, the nitriding of the high dielectric constant film can be conducted while maintaining the compatibility of the suppression of an increase in interface level density and the suppression of generation of fixed electric charges. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了形成其中在硅半导体衬底的表面和作为含有金属和硅氧烷的高介电常数材料的氧氮化物膜的表面之间设置氧化膜或氧氮化物膜的结构，以便抑制可以兼容接口电平密度的增加和固定电荷产生的抑制。解决方案：为了抑制硅半导体衬底的不期望的氮化，在高介电常数材料膜和硅衬底之间的界面上形成1nm以下的氧化硅膜或氧氮化物膜是有效的。然而，在界面层和高介电常数材料膜之间的界面上产生电荷，由于电荷而不能实现迁移率的提高。在硅半导体基板1的表面上沉积含有金属元素和硅酮元素的高介电常数材料的膜2，然后从高介电常数材料的上方进行界面氧化3，介电常数材料经受氮化4.通过高介电常数材料的膜上的界面氧化，可以进行高介电常数膜的氮化，同时保持抑制界面能级密度增加和抑制固定电费的产生。版权所有（C）2005，JPO＆NCIPI

45. 发明专利

JP2001257344A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001257344A
公开(公告)日：2001-09-21
申请号：JP2000066960
申请日：2000-03-10
申请人： TOSHIBA CORP
发明人： TSUNASHIMA YOSHITAKA , INUMIYA SEIJI , MINAZU YASUMASA , OZAWA YOSHIO , MIYANO KIYOTAKA , TANAKA MASAYUKI
IPC分类号： H01L21/283 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8234 , H01L29/49 , H01L29/51 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device which uses a metal oxide film or a metal silicate film as a gate insulating film. SOLUTION: An insulating film 6 which includes a metal, silicon and oxygen, is formed between a semiconductor substrate 1 and a metal oxide film 3. The insulating film 6 which includes a metal, silicon and oxygen includes either fluorine or nitrogen at least. The metal oxide film 3 and the insulating film 6 including a metal, silicon and oxygen are amorphous films. The main metal element composing the metal oxide film 3 which is different from the main metal element composing the insulating film 6 may include metal, silicon and oxygen, there is no problem.

46. 发明专利

JPH11251581A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11251581A
公开(公告)日：1999-09-17
申请号：JP4941498
申请日：1998-03-02
申请人： TOSHIBA CORP
发明人： INUMIYA SEIJI , OZAWA YOSHIO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, whereby punch-throughs and narrow channel effects and reduction in the dielectric strength of a gate insulation film can be prevented and trenches can be formed self-aligningly. SOLUTION: A gate oxide film 1 and a first polycrystalline Si film 3 are formed successively on a p-type well 1, and after the first polycrystalline Si film 3 is etched to form a gate electrode 3, using a pattern 5 defining an island- like element-forming region as a mask, nitrogen is introduced in the side face of the gate electrode 3 as an oxidation suppressing material. Then, the p-type well 1 is etched to form a trench 7 self-aligningly with the gate electrode 3, using the pattern 5 as a mask. Thereafter, as normal, an element isolating insulation film and gate lead-out electrode are formed.

47. 发明专利

JPH1174508A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH1174508A
公开(公告)日：1999-03-16
申请号：JP18530198
申请日：1998-06-30
申请人： TOSHIBA CORP
发明人： INUMIYA SEIJI , OZAWA YOSHIO , HIEDA KATSUHIKO , MATSUDA TETSURO
IPC分类号： H01L29/78 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To solve problems which arise when a gate electrode is formed through a gate insulating film on an area from which a dummy gate pattern and a dummy insulating film are eliminated. SOLUTION: A method for manufacturing a semiconductor device is composed of a process for forming a dummy film 13 and a dummy gate pattern 14 on an area for forming a gate on a semiconductor substrate, a process for forming first a side wall insulating film 15 on the side walls of the dummy gate pattern 14, a process for forming an interlayer insulating film 18 on the semiconductor substrate around the dummy gate pattern 14 with the first side wall insulating film 15, a process for forming a groove 30 by eliminating the dummy pattern 14, a process for eliminating the dummy film 13 exposed in the groove 30 in such a way that a part of the first side wall insulating film 15 and the part of the dummy film 13 under it are left, a process for forming a gate insulating film at least in the bottom of the groove and a process for forming a gate electrode on the gate insulating film in the groove.

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