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41. 发明专利

JP2001211424A DIGITAL SIGNAL PROCESSING UNIT 失效
公开(公告)号：JP2001211424A
公开(公告)日：2001-08-03
申请号：JP2000019558
申请日：2000-01-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KASHIRO TAKAO , YANO KATSUHISA , YASUE TAKESHI
IPC分类号： H04N5/94 , H04N5/92
摘要： PROBLEM TO BE SOLVED: To provide a digital signal processing unit that can reduce deterioration in image quality of are produced image and malfunction of a decoder where a variable length code is decoded with respect to error processing in the case of producing the video signal digitally processed, variable length coded and recorded on a recording tape medium or the like. SOLUTION: In the case of reproducing a video signal or the like that is digitized, variable length coded and recorded on a recording tape medium, packet data whose error is detected are generated and outputted to a decoder.

42. 发明专利

JPH11331846A VIDEO SIGNAL PROCESSOR 失效
公开(公告)号：JPH11331846A
公开(公告)日：1999-11-30
申请号：JP7227499
申请日：1999-03-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YASUE TAKESHI , YANO KATSUHISA , KASHIRO TAKAO , MURATA HISAHARU
IPC分类号： H04N19/60 , G11B20/10 , H04N19/107 , H04N19/126 , H04N19/132 , H04N19/134 , H04N19/172 , H04N19/196 , H04N19/625 , H04N19/85 , H04N19/91 , H04N7/30
摘要： PROBLEM TO BE SOLVED: To reduce a data quantity without deteriorating a reproduced picture with respect to variable length coded word data by providing a means removing specific components in coded data. SOLUTION: At the time of inputting a first discrete cosine transformation(DCT) coefficient, an inverse quantization means 103 obtains a first quantized matrix from a first quantizing matrix means 104 to execute inverse quantizing processing on the first DCT coefficient to generate inverse quantization data and outputs it to a quantizing means 105. A second quantizing matrix means 106 keeps a second quantized matrix and at the time of inputting inverse quantization data, the means 105 obtains the second quantized matrix by a second quantizing matrix means 106 to execute quantizing processing with respect to inverse quantization data to generate a second DCT coefficient. In this case, the second quantized matrix is set to make the value zero with respect to many high-pass AC components compared with the first quantized matrix.

43. 发明专利

JP2548135B2 失效
公开(公告)号：JP2548135B2
公开(公告)日：1996-10-30
申请号：JP14530986
申请日：1986-06-20
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KASHIRO TAKAO
IPC分类号： G11B27/00 , G11B27/02 , G11B27/024 , G11B27/10 , G11B27/28 , H04N5/78

44. 发明专利

JPH0738776A VIDEO SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH0738776A
公开(公告)日：1995-02-07
申请号：JP17898293
申请日：1993-07-20
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIDAKA IWAO , KASHIRO TAKAO
IPC分类号： G06F1/32 , G06F1/04 , H04N5/14
摘要： PURPOSE:To sharply reduce power consumption by a small-scaled circuit by providing a circuit constitution in which data of a period which is not necessary at a signal processing circuit are not processed. CONSTITUTION:This circuit is equipped with a data invarying circuit 3 which outputs data of the period which is necessary for a signal processing among inputted data without operating a data processing, and outputs the data of the period which is not necessary for the signal processing by fixing the data to an arbitrary value. Then, when the data inputted from an input terminal 1 are the data of the period which is necessary at a signal processing circuit 4, the data invarying circuit 3 outputs the data without processing the data, and when the data are the data of the period which is not necessary at the signal processing circuit 4, the data invarying circuit 3 outputs the data by fixing the data to an arbitrary value (High or Low), or outputs data by holding the final data of the necessary data. The signal processing circuit 4 performs an arithmetic processing necessary for recording by using the data outputted from the data invarying circuit 3, and outputs the data from an output terminal 5.

45. 发明专利

JPH0723345A TIME BASE CORRECTING DEVICE 失效
公开(公告)号：JPH0723345A
公开(公告)日：1995-01-24
申请号：JP14889693
申请日：1993-06-21
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KASHIRO TAKAO , HASHIMOTO SEIICHI
IPC分类号： G11B20/02 , G11B20/06 , H03L7/22 , H04N5/92 , H04N5/937 , H04N5/956 , H04N7/24 , H04N19/00 , H04N19/42 , H04N19/423 , H04N19/80 , H04N19/85
摘要： PURPOSE:To reduce the scale of a time base correcting circuit by enabling a memory to be variable the phase relation between the writing timing of data and the reading timing thereof in a certain degree. CONSTITUTION:A clock and a reference signal whose phase is synchronized with that of a horizontal synchronizing signal is outputted from a Hi-PLL circuit in a clock and reference signal generating circuit 10. An ADC 1 converts an input signal into a digital signal by using a clock outputted from the circuit 10. A control circuit 5 generates a write control signal for an FIFO 3 in accordance with the 1st clock and a horizontal reference signal outputted from the circuit 10. A data processing circuit 2 executes the data processing of the input signal in accordance with the control signal generated from the circuit 5 and writes the processed data in the FIFO 3. The circuit 5 outputs also reference signal for determining the reading timing of the FIFO 3. Reading from the FIFO 3 and writing in a picture memory 4 are a series of operation and processed by the 2nd clock generated by a Lo-PLL in the circuit 10. Thereby a conversion circuit 6 synchronizes the FIFO reading reference signal outputted from the circuit 5 with I/O operation in/from the memory 4.

46. 发明专利

JPH05344472A 失效
公开(公告)号：JPH05344472A
公开(公告)日：1993-12-24
申请号：JP25954192
申请日：1992-09-29
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OTAKA HIDEKI , KASHIRO TAKAO
IPC分类号： G11B20/10 , G11B20/12 , H04N5/92 , H04N5/93 , H04N5/937
摘要： PURPOSE:To realize slow reproduction in the unit of fields in the digital VTR in which a signal is subjected to high efficiency coding in the unit of plural fields and recorded. CONSTITUTION:A frame detector 102 detects the end of data reproduction for one frame from address information 5 and after one frame data are written in a memory 106, a frame switching signal 103 is set to set switches 108, 109 to an L level. Thus, a memory 106 and a memory control circuit 110 implement read operation and a memory 107 and a memory control circuit 111 implement write operation, data are read from the memory 106 from a succeeding frame period and the data are written in the memory 107. As to read in the unit of fields, a field switching signal is set to an H level, the data of a 0th field are repetitively read from the memory 106 for each field period, a field detector 104 sets a succeeding field switching signal to an L level after the end of data reproduction by one field is detected from the succeeding frame and the data of the 1st field are read repetitively from the memory 106.

47. 发明专利

JPH05183868A ADDRESS GENERATION DEVICE 失效
公开(公告)号：JPH05183868A
公开(公告)日：1993-07-23
申请号：JP34481891
申请日：1991-12-26
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MICHIMASA SHIRO , KASHIRO TAKAO
IPC分类号： H04N5/907 , G06T1/00 , H04N5/92
摘要： PURPOSE:To return the address generation device to a correct shuffling state by detecting an error in the address of picture element data generated at the time of the shuffling owing to a noise, etc. CONSTITUTION:An FIFO memory 1 is stored with a read address for picture element data in a frame memory 50 as to a current frame. An address determination part 30 sets a read address of the frame memory 50 for a next frame according to the output signal 1a of the FIFO memory 1 and writes it as an output signal 2a in the FIFO memory 1 sequentially. An address decision part 40 inputs the output signal 2a and logic data '1' or '0' which is inverted at intervals of one frame of a video signal. Then a D-FF 13 outputs an output signal 16 as a reset signal to the address determination part 30 unless the output signal 14 of an address checking memory 51 coincides with logic data 17a from a multiplexer 17.

48. 发明专利

JPH04159886A VIDEO SIGNAL PROCESSOR 失效
公开(公告)号：JPH04159886A
公开(公告)日：1992-06-03
申请号：JP28673190
申请日：1990-10-23
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KASHIRO TAKAO
IPC分类号： H04N5/7826 , H04N5/782 , H04N5/783 , H04N5/93 , H04N5/937
摘要： PURPOSE:To display reproduced signals on a monitor screen at various tape speeds by fixing the running speed of a magnetic tape and correcting the relative speed between the running speed of the magnetic tape and the rotating speed of a cylinder at the time of quick-traversing reproduction and rewinding reproduction. CONSTITUTION:When a magnetic tape 5 is run at a high speed, signals obtained from speed detectors 13 and 14 are inputted to capstan control/driving circuit 16 to control a capstan motor 8 so that the running speed of the tape 5 can be fixed to a constant speed. In addition, the relative speed between a cylinder 2 and tape 5 is read out from a ROM 18 and compared with the signals of a speed and phase detectors 3 and 4 and the rotating speed of the cylinder 2 is controlled to obtain the same relative speed value as that of the ROM 18 by means of a cylinder control/driving circuit 15 so that the horizontal feedback period of reproduced signals can become the same as that of the normal reproduction time. Thus the relative speed between the cylinder 2 and tape 5 is corrected even when the tape 5 is run at a high speed. Therefore, the horizontal feedback period of the reproduced signals can be maintained under the same condition and picture can be reproduced normally even when the tape 5 is run at a high speed.

49. 发明专利

JPH03250876A VIDEO SIGNAL DISPLAY DEVICE 失效
公开(公告)号：JPH03250876A
公开(公告)日：1991-11-08
申请号：JP4760790
申请日：1990-02-28
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KASHIRO TAKAO , OISHI YOSHINOBU , KAMATA SHINYA
IPC分类号： H04N5/45
摘要： PURPOSE:To display 1st and 2nd video images without a blank automatically corresponding to the 1st video image written in an optional range by storing the end of write of the 1st video signal by a latch circuit and allowing a comparator decoder circuit to discriminate the readout over the write and selecting the display of the 2nd video signal. CONSTITUTION:A control signal output of a comparator decoder circuit 16 resulting from a write address and a readout address latched by a latch circuit 15 is used for changeover control of a video signal switching circuit 12. The latch circuit 15 latches and stores an address just before the write address is reset and the comparator decoder circuit 16 compares the quantity between the readout address and the latched address and outputs a switching control signal when the readout address is larger than the latched address. Thus, the 1st and 2nd video signals are switched and displayed without a blank corresponding to the 1st video signal written in an optional range.

50. 发明专利

JPH035903A COLOR SIGNAL NOISE REMOVING DEVICE FOR VCR 失效
公开(公告)号：JPH035903A
公开(公告)日：1991-01-11
申请号：JP14172989
申请日：1989-06-02
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： USUKI NAOJI , KASHIRO TAKAO
IPC分类号： H04N5/21 , G11B5/027 , H04N5/93 , H04N9/87
摘要： PURPOSE:To increase a noise removing effect and to decrease after-images by providing a switching means for switching and outputting a 1st correction value and a 2nd correction value. CONSTITUTION:The 1st correction value and the 2nd correction value are automatically switched and outputted by the recording mode of a reproduction color signal. The optimized correction value is added to reproduction color signal and outputted it to adding means. Namely, correction value generators 7, 10 are constituted of level converters 9 and 12 as well as limiters 8 and 11. The correction value switch 6 switches the correction values outputted from the correction value generators 7 and 10 and a recording mode detector 5 outputs a switching signal by detecting the recording mode of the reproduction color signal from a tape speed control system, etc., and applies the same to the correction value switch 6. The noises are stably and surely removed in this way and the trouble by the after-images is minimized.

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