专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

JPH09219484A MANUFACTURE OF SUBSTRATE FOR LOADING ELECTRONIC COMPONENT 失效
公开(公告)号：JPH09219484A
公开(公告)日：1997-08-19
申请号：JP4807996
申请日：1996-02-09
申请人： IBIDEN CO LTD
发明人： KARIYA TAKASHI
IPC分类号： H01L23/50
摘要： PROBLEM TO BE SOLVED: To provide the manufacture of a substrate capable of accurately forming a bent stepped section to a lead as thickness original in the lead is left as it is kept and being used for loading an electronic part. SOLUTION: When bent stepped sections are formed to a large number of leads 10, in which joining end sections 11 are joined with a conductor circuit in the periphery of a substrate 2, the joining end sections 11 of the leads 10 are connected to the lands of through-holes formed to the substrate 2. Bending forming sections 120 for forming the bent stepped sections are bent beforehand in the direction orthogonal to the bending direction of the bent stepped sections regarding the leads. The leading-out sections 13 of the leads are arranged between the plane section of a top force 31 and the plane section of a bottom force. Pushing load is applied to the substrate 2 by a punch, the bending forming sections in the leads are curved in the thickness direction of the bending forming sections, the leads are deformed in a 'chevron' shape along the thickness direction, and the bent stepped sections are formed.

42. 发明专利

JP2014229698A 配線板及び配線板の製造方法审中-公开
标题翻译：接线板及其制造方法
公开(公告)号：JP2014229698A
公开(公告)日：2014-12-08
申请号：JP2013107178
申请日：2013-05-21
申请人：イビデン株式会社 , Ibiden Co Ltd
发明人： KARIYA TAKASHI , KANNO YOSHINORI , TERUI MAKOTO , KUNIEDA MASATOSHI
IPC分类号： H05K3/46
CPC分类号： H05K3/4682 , H05K3/0035 , H05K3/3436 , H05K3/4694 , H05K2201/10159
摘要：【課題】製品の製造コストを削減する。【解決手段】DRAM60が接続されるパッドP2が形成された配線構造体50を、配線板10の最も上側の絶縁層21の内部に設ける。そして、この配線構造体50のパッドP2の外径を、MPU70が接続されるパッドP1の外径よりも小さくし、パッドP2の配列間隔を、パッドP1の配列間隔よりも小さくする。これにより、配線板10全体の導体パターン31〜35をファインピッチ化することなく、DRAM60が実装される部分の導体パターン54,55をファイン化することができる。したがって、配線板10の製造コストを削減することができる。【選択図】図1
摘要翻译：要解决的问题：降低产品的制造成本。解决方案：在布线板10的最上层绝缘层21中设置有用于与DRAM60连接的焊盘P2的布线结构50。外径布线结构50中的焊盘P2的位置被设定为小于与MPU 70连接的焊盘P1的外径，并且焊盘P2的布置间隔被设定为小于焊盘P1的布置间隔。因此，可以使安装有DRAM60的部分的导体图形54,55精细，而不需要以细间距布置布线板10上的全部导体图案31-35。因此，可以减少布线板10的制造成本。

43. 发明专利

JP2012033968A Printed wiring board and method of manufacturing the same 审中-公开
标题翻译：印刷线路板及其制造方法
公开(公告)号：JP2012033968A
公开(公告)日：2012-02-16
申请号：JP2011238996
申请日：2011-10-31
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , MOCHIDA AKIYOSHI
IPC分类号： H05K3/46 , H01L23/12
CPC分类号： H01L21/6835 , H01L21/4857 , H01L2221/68345 , H01L2221/68363 , H01L2224/05001 , H01L2224/16 , H01L2224/16235 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H05K1/162 , H05K3/4602 , H05K2201/0175 , H05K2201/0355 , H05K2201/09309 , H05K2201/09509 , H05K2201/09518 , H05K2201/09718 , H05K2203/0353 , Y10T29/435 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board capable of forming a capacitor part in the flow of buildup.SOLUTION: In a printed wiring board 10, the upper electrode connection first part 52a of an upper electrode connection 52 penetrates a capacitor 40 in the vertical direction without touching the capacitor 40, and is connected with an upper electrode 42 from the upper electrode connection second part 52b via the upper electrode connection third part 52c provided above the capacitor 40. A lower electrode connection 51 penetrates the capacitor 40 in the vertical direction so that it does not touch the upper electrode 42 but touches a lower electrode 41. Consequently, the upper electrode connection 52 and the lower electrode connection 51 can be formed, in the flow of buildup, even after the entire surface is covered with a high dielectric capacitor sheet having such a structure as a high dielectric layer is sandwiched by two metal foils and becoming the capacitor 40 later.
摘要翻译：要解决的问题：提供能够在积聚流中形成电容器部分的印刷线路板。解决方案：在印刷电路板10中，上电极连接52的上电极连接第一部分52a在垂直方向上穿过电容器40而不接触电容器40，并且从上部电极连接到上电极42 电极连接第二部分52b经由设置在电容器40上方的上电极连接第三部分52c。下电极连接件51在垂直方向上穿透电容器40，使得它不接触上电极42但接触下电极41.因此即使在整个表面被具有高电介质层的结构的高介电电容器片覆盖的两个金属箔夹着的情况下，也可以形成上电极连接部52和下电极连接部51 并且稍后变成电容器40。版权所有（C）2012，JPO＆INPIT

44. 发明专利

JP2007243214A Multilayer circuit board 审中-公开
标题翻译：多层电路板
公开(公告)号：JP2007243214A
公开(公告)日：2007-09-20
申请号：JP2007121221
申请日：2007-05-01
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： ASAI MOTOO , KARIYA TAKASHI , SHIMADA KENICHI , SEGAWA HIROSHI
IPC分类号： H05K3/46 , H05K3/28
摘要： PROBLEM TO BE SOLVED: To provide a multilayer circuit board advantageous for densification of through-holes which can fully secure electrical connections to an inner layer circuit within a core substrate, even if the core substrate is processed in multilayer. SOLUTION: In the multilayer circuit board with a multilayer core substrate having a conductor layer in inner layer, the through-holes each having a land exposed on the core substrate front surface are formed in the multilayer core substrate, and a filling material is filled up in each through-hole, and the conductor layer, which is located directly upward from the land, is formed by a non-electrolytic plating film and electrolytic plating film. A via hole is connected to the electrolytic plating film, and the non-electrolytic plating film is contacted with the filling material, and rough processed layers are formed in a side of the through-hole land, and a side and top of the conductor layer formed directly upward from the land, and the rough processed layers are formed in a side and top of the other conductor layer located within the same plane as the conductor layer. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使核心基板被加工成多层的方式，提供了一种有利于通孔致密化的多层电路板，该通孔可完全确保与芯基板内的内层电路的电连接。解决方案：在具有在内层中具有导体层的多层芯基板的多层电路板中，在多层芯基板上形成各自具有露出在芯基板前表面上的焊盘的通孔，并且填充材料填充在每个通孔中，并且通过非电解镀膜和电解电镀膜形成位于从地面直接向上的导体层。通孔连接到电解镀膜，非电解镀膜与填充材料接触，并且在通孔焊盘的一侧形成粗加工层，并且导体层的侧面和顶部从地面直接向上形成，并且粗加工层形成在位于与导体层相同的平面内的另一导体层的侧面和顶部。版权所有（C）2007，JPO＆INPIT

45. 发明专利

JP2007165381A Method of manufacturing printed wiring board having component mounting pin 有权
标题翻译：制造具有组件安装PIN的印刷电路板的方法
公开(公告)号：JP2007165381A
公开(公告)日：2007-06-28
申请号：JP2005356119
申请日：2005-12-09
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , FURUYA TOSHIKI , KASAI TAKESHI
IPC分类号： H05K3/34
CPC分类号： H05K3/4092 , H05K2201/0311 , H05K2203/308 , Y10T29/49124 , Y10T29/49155 , Y10T29/49156
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a printed wiring board having a component mounting pin for connecting a printed wiring board and an electronic component. SOLUTION: In the method of manufacturing the printed wiring board (1) having the component mounting pin (18) has a step of forming a component mounting surface after forming the predetermined number of layers. This step includes processes of forming a conductor land (11) on the component mounting surface, covering the component mounting surface other than a portion of the conductor land with an insulation layer (12), partially forming a sacrificial layer (14) removable in a post process in the vicinity of the conductor land on the upper surface of the insulation layer, forming conductor layers (16, 17) on the top surfaces of the conductor land and the sacrificial layer and pattering the conductor layers, partially removing the sacrificial layer (14) positioned below the patterned conductor layers (16, 17) to form the component mounting pin (18) extending from the conductor land, and erecting the component mounting pin. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有用于连接印刷线路板和电子部件的组件安装销的印刷线路板的制造方法。解决方案：在制造具有元件安装销（18）的印刷电路板（1）的方法中，具有在形成预定数量的层之后形成部件安装表面的步骤。该步骤包括在部件安装表面上形成导体焊盘（11）的工艺，用绝缘层（12）覆盖除了导体焊盘的一部分之外的部件安装表面，部分地形成牺牲层（14）在绝缘层的上表面上的导体接合区附近进行后处理，在导体焊盘和牺牲层的顶表面上形成导体层（16,17）并对导体层进行图案，部分地去除牺牲层（ 14）定位在图案化的导体层（16,17）下方，以形成从导体接合部延伸的部件安装销（18），并且架设部件安装销。版权所有（C）2007，JPO＆INPIT

46. 发明专利

JP2006210776A Package substrate with built-in capacitor and its manufacturing method 有权
标题翻译：具有内置电容器的封装基板及其制造方法
公开(公告)号：JP2006210776A
公开(公告)日：2006-08-10
申请号：JP2005022992
申请日：2005-01-31
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI
IPC分类号： H01L23/12 , H05K3/46
CPC分类号： H01G4/30 , H01G4/232 , H01L23/49822 , H01L23/50 , H01L23/66 , H01L24/16 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/16235 , H01L2224/16237 , H01L2224/81192 , H01L2224/8121 , H01L2224/81815 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/01057 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H05K1/113 , H05K1/162 , H05K3/4652 , H05K2201/0175 , H05K2201/09518 , H05K2201/096 , H05K2201/09718 , H05K2203/0152 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To keep capacitor's performance even if electrodes of a thin film capacitor are short-circuited. SOLUTION: If a first thin and small electrode 41aa and a second thin and small electrode 42aa which are electrically short-circuited via a pin hole P of a highly dielectric material layer 43 are present, the first electrode 41aa has no power supply post 61a nor via hole 61b formed, and the second electrode 42aa has no ground post 62a nor via hole 62b formed. As a result, any of small electrodes 41aa and 42aa which are short-circuited are not electrically connected with a power supply line nor a ground line, having a potential independent from the power supply potential and the ground potential. Therefore, only parts of both short-circuited electrodes 41aa and 42aa of the thin film capacitor 40 sandwiching the highly dielectric material layer 43 lose the function as a capacitor, while other parts of thin and small electrodes 41a and 42a sandwiching the layer 43 keep the function as a capacitor. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了保持电容器的性能，即使薄膜电容器的电极短路。解决方案：如果存在经由高介电材料层43的针孔P电短路的第一薄电极41aa和第二薄电极42aa和第二小电极42aa，则第一电极41aa没有电源柱61a或通孔61b，并且第二电极42aa没有形成接地柱62a和通孔62b。结果，任何短路的小电极41aa和42aa都不与电源线和地电位无关的电源线和接地线电连接。因此，仅夹着高电介质材料层43的薄膜电容器40的短路电极41aa和42aa的一部分作为电容器失去功能，而夹着层43的薄电极41a和小电极42a的其他部分保持用作电容器。版权所有（C）2006，JPO＆NCIPI

47. 发明专利

JP2006066597A Printed wiring board 有权
标题翻译：印刷线路板
公开(公告)号：JP2006066597A
公开(公告)日：2006-03-09
申请号：JP2004246651
申请日：2004-08-26
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , FURUYA TOSHIKI
IPC分类号： H01L23/12 , H05K3/46
CPC分类号： H01L2224/16225 , H01L2924/15174 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board capable of preventing a connection with an electronic component from being broken owing to heat expansion or heat shrinkage and stably supplying electric power to the electronic component. SOLUTION: On the printed wiring board 10, a conductor post 34 has a solder core body 37 differently from a conventional conductor post made of copper nearly entirely. In general, solder is lower in coefficient of elasticity (e.g. Young's modulus) than copper, so the conductor post 34 never greatly hinders elastic deformation of a stress relaxation layer 30. Further, a barrier layer 36 brings the solder core body 37 and stress relaxing layer 30 into contact with each other, so when the stress relaxation layer 30 elastically deforms, the solder core body 37 and stress relaxation layer 30 never peels off each other. Therefore, even if stress is generated due to a difference in thermal expansion between a core substrate 12 and an IC chip 50, the stress is securely relaxed by the stress relaxation layer 30, and peeling from which cracking easily originates is not caused. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够防止与电子部件的连接由于热膨胀或热收缩而破裂并且稳定地向电子部件供电的印刷线路板。解决方案：在印刷电路板10上，导体柱34具有与几乎完全由铜构成的常规导体柱不同的焊料芯体37。通常，焊料的弹性系数（例如杨氏模量）低于铜，因此导体柱34从不会大大地阻碍应力松弛层30的弹性变形。此外，阻挡层36使焊料芯体37和应力放松层30彼此接触，因此当应力松弛层30弹性变形时，焊料芯体37和应力松弛层30不会剥离。因此，即使由于芯基板12和IC芯片50之间的热膨胀差异而产生应力，应力松弛层30可以使应力松弛，也不会引起容易产生龟裂的剥离。版权所有（C）2006，JPO＆NCIPI

48. 发明专利

JP2005123548A Interposer and multilayer printed wiring board 审中-公开
标题翻译：插件和多层印刷接线板
公开(公告)号：JP2005123548A
公开(公告)日：2005-05-12
申请号：JP2003381049
申请日：2003-11-11
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , FURUYA TOSHIKI
IPC分类号： H01L23/32
摘要： PROBLEM TO BE SOLVED: To provide an interposer that can prevent the disconnection of a wiring pattern on an IC chip mounted on a package substrate.
SOLUTION: The stress caused by the difference between the coefficients of thermal expansion of a multilayer printed wiring board 10 having a large coefficient of thermal expansion and the IC chip 110 having a small coefficient of thermal expansion can be absorbed by interposing the interposer 70 between the package substrate 10 and IC chip 110.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以防止安装在封装基板上的IC芯片上的布线图案断开的插入件。解决方案：具有大的热膨胀系数的多层印刷电路板10的热膨胀系数与具有小的热膨胀系数的IC芯片110之间的差异导致的应力可以通过插入插入件 70在封装基板10和IC芯片110之间。（C）2005，JPO＆NCIPI

49. 发明专利

JP2005123546A Interposer and multilayer printed wiring board 审中-公开
标题翻译：插件和多层印刷接线板
公开(公告)号：JP2005123546A
公开(公告)日：2005-05-12
申请号：JP2003381046
申请日：2003-11-11
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , FURUYA TOSHIKI
IPC分类号： H01L23/32
CPC分类号： H01L2224/16225 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide an interposer that can prevent the disconnection of a wiring pattern on an IC chip mounted on a package substrate. SOLUTION: The stress caused by the difference between the coefficients of thermal expansion of a multilayer printed wiring board 100 having a large coefficient of thermal expansion and an IC chip 110 having a small coefficient of thermal expansion can be absorbed by interposing the interposer 70 between the package substrate 10 and IC chip 110. Particularly, the stress is absorbed in the interposer 70 by using a material (having a Young's modulus of 0.010-1.0 GP) which is softer than the IC chip 110 and package substrate 10 as the insulating substrate 80 constituting the interposer 70. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以防止安装在封装基板上的IC芯片上的布线图案断开的插入件。解决方案：具有大的热膨胀系数的多层印刷线路板100的热膨胀系数与具有小的热膨胀系数的IC芯片110之间的热膨胀系数的差引起的应力可以通过插入插入件特别地，通过使用比IC芯片110和封装基板10更柔软的材料（具有0.010-1.0GP的杨氏模量）的材料，吸收插入件70中的应力作为内插基板10。绝缘基板80构成内插器70.版权所有（C）2005，JPO＆NCIPI

50. 发明专利

JP2004079554A Single-sided circuit board and method of manufacturing the same 审中-公开
公开(公告)号：JP2004079554A
公开(公告)日：2004-03-11
申请号：JP2002214362
申请日：2002-07-23
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , TAMAKI MASANORI
IPC分类号： H05K1/11 , H01L23/12 , H05K3/00 , H05K3/06 , H05K3/40 , H05K3/46
CPC分类号： H01L2924/15174
摘要： PROBLEM TO BE SOLVED: To provide single-sided circuit boards for composing a multilayer circuit board having high electrical reliability. SOLUTION: A plurality of bottlenecks 18a are provided to the side walls of via holes 18 of the single-sided circuit boards A, B1, B2, B3, and B4, so that the contacting surface of an insulating board 10 with the via hole 18 can be increased in area, and the adhesion of the insulating board to the via hole 18 can be improved. Stress generated when the single-sided circuit boards A, B1, B2, B3, and B4 are laminated and bonded together by pressure can be relaxed. When the single-sided circuit boards A, B1, B2, B3, and B4 are pressed (pressure-bonding), stress conducted to the inside and outside of the via hole 18 is buffered by the bottlenecks 18b, and the attenuated stress is conducted as a whole, so that cracking and fracture hardly occur in the multilayer circuit board. COPYRIGHT: (C)2004,JPO

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式