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41. 发明专利

JPH04223566A NUMERIC VALUE RETRIEVAL APPARATUS 失效
公开(公告)号：JPH04223566A
公开(公告)日：1992-08-13
申请号：JP40653990
申请日：1990-12-26
申请人： HITACHI LTD
发明人： SHIMURA TAKANORI , KAWAGUCHI HISAMITSU , KATO KANJI
IPC分类号： G06F5/00 , G06F17/30
摘要： PURPOSE:To provide an numeric value retrieval apparatus for retrieving all the numeric values of a document that can retrieve not only Arabic numerals in the document, but also Kanji numerals. CONSTITUTION:The present numeric value retrieval apparatus is provided with a code conversion means (50) for converting Kanji numerals (Chinese numerals) in character strings to be retrieved into Arabic numerals coded in good order, a range information storage means (3) for storing a state transition condition of finite automation as a range of character codes, and a retrieved character storage means (10) for storing character that specifies digit of a Kanji numeral, wherein a Kanji numeral is retrieved by finite automata (1, 2, 9, 11) causing state transition as a result of comparison between retrieval object character strings that are converted into codes, the output from the range information storage, and the output from the retrieved character storage means.

42. 发明专利

JPH0370216A ADAPTIVE FILTER FOR ELIMINATING MULTI-PATH FADING 失效
公开(公告)号：JPH0370216A
公开(公告)日：1991-03-26
申请号：JP20461289
申请日：1989-08-09
申请人： HITACHI LTD , YUSEISHO TSUSHIN SOGO KENK
发明人： SHIMURA TAKANORI , TSUKAMOTO NOBUO , USUI KUNITO , OKANE TAKEO , SASAOKA SHUICHI , SANPEI MASAICHI , KAMIO YUKIHIDE
IPC分类号： H04B7/005 , H03H21/00 , H04B1/10
摘要： PURPOSE:To process a reception data at high speed and to eliminate noise of multi-path fading at high speed by receiving information simultaneously with one bus cycle of master digital signal processing with use of a temporary storage means. CONSTITUTION:When a data is transferred from digital signal processors(DSP) 2-4 to a DSP 1, the DSP 2-4 transfer a data to first-in first-out memories(FIFO) 5, 7, 9, and it is required for the DSP 1 to read sequentially data y2-y4 from FIFOs 5, 7, 9, but when the data is transferred to the DSP 2-4, the data 20 is written from the DSP 1 in one bus cycle to the FIFOs 6, 8, 10 simultaneously. Thus, the DSP 2-4 read data from the FIFOs 6, 8, 10 simultaneously respectively. Thus, nose due to multi-path fading is eliminated at high speed.

43. 发明专利

JPH01128338A SURFACE OBSERVER 失效
公开(公告)号：JPH01128338A
公开(公告)日：1989-05-22
申请号：JP28325687
申请日：1987-11-11
申请人： HITACHI LTD
发明人： SHIMURA TAKANORI , KAWANAMI YOSHIMI , ISHITANI TORU , UMEMURA KAORU , MITSUI YASUHIRO
IPC分类号： G01B15/00 , G01B15/08 , H01J37/22 , H01J37/244
摘要： PURPOSE:To make a clear-cut image displayable at high speed by setting up a bit mask circuit, nullifying a bit inclusive of noise, in secondary electron data collector part, and installing a color lookup table circuit, capable of selecting optional several colors, in an image display part. CONSTITUTION:Prior to starting a data collection, a main control part 1 specifies a gain of a gain control part 15. A beam 5 is subjected to test scanning and, after gain setting is over, whether what degree of a noise component is in secondary electron data is checked. Next, the main control part 1 indicates a bit mask circuit 18 that how many subordinate bits should be nullified. With this indication, the bit mask circuit 18 removes the specified noise component. In addition, a color lookup table 27 specifies a display color corresponding to intensity of a secondary electron. When it wants to emphasize an optional part, this case will be done by rewriting of the color lookup table. With this constitution, the optional part on a sample can be emphasized and displayed by only collecting the secondary electron intensity data discharged out of the sample one time.

44. 发明专利

JPS6394623A DEVICE FOR PATTERN GENERATION 失效
公开(公告)号：JPS6394623A
公开(公告)日：1988-04-25
申请号：JP23900586
申请日：1986-10-09
申请人： HITACHI LTD
发明人： OYAMA MITSUO , ANDO MASAAKI , KAWAMURA YOSHIO , SAITO NORIO , SHIMURA TAKANORI , KOHIDA HIROYUKI
IPC分类号： G02B5/18 , H01J37/302 , H01J37/305 , H01J37/317 , H01L21/027
摘要： PURPOSE:To enable a high speed pattern drawing to be performed without decomposing a specific figures by a method wherein contours of drawn figure are stored in a contour memory to be scanned while only the contour inside of figure is irradiated with beams. CONSTITUTION:A pattern drawing sequence control circuit 6 transmits selective control signals 206 to a multiplexor 7 to select addresses of contour memory produced by a contour writing-in circuit 3 for writing contours in the contour memory in dot image. The sequence control circuit 6 controls the selective signals 206 to start a pattern scanning circuit 5 after selecting the addresses outputted by the scanning circuit 5. Thus, the contour memory is scanned while producing a beam deflection address corresponding to the contour memory scanning to be converted by DA converters 8, 9 for scanning the beams. Furthermore, the pattern scanning circuit 5 controls beam blanking signals 211 to irradiate only the contour side with beams so that the contour inside of a drawn figure may be painted out to draw a specified figure.

45. 发明专利

JPS615622A DYNAMIC OPERATION TYPE PLA 失效
公开(公告)号：JPS615622A
公开(公告)日：1986-01-11
申请号：JP12513384
申请日：1984-06-20
申请人： HITACHI LTD
发明人： SHIMURA TAKANORI , FUNABASHI TSUNEO , YAMAGUCHI NOBORU , IWASAKI KAZUHIKO , TATEZAKI JIYUNICHI
IPC分类号： H03K19/177
摘要： PURPOSE:To uniform the timing of a control signal and to facilitate logical design and circuit design by adding a clock of the 3rd phase to control clocks newly. CONSTITUTION:The clock phi3 of the 3rd phase is generated by delaying the rise of a clock phi1 and shorten the width of the ''1'' period of the clock phi1. Namely, the clock phi3 rises after the output signal 26a of a phi1 synchronism processing circuit 26 is established. The use of phi3 allows the input signal 26a of a phi1 synchronized dynamic operation type PLA37 to be used as the input signal of an AND35 while phi3 is 1. Then, phi1 and phi3 rise at the same timing, so the input timing of the AND surface 35 is the same with phi1. Thus, the timing of a control signal is made uniform, so the logical design and circuit design are facilitated.

46. 发明专利

JPS60183670A SERIAL DATA PROCESSING UNIT 失效
公开(公告)号：JPS60183670A
公开(公告)日：1985-09-19
申请号：JP3854084
申请日：1984-03-02
申请人： HITACHI LTD
发明人： SHIMURA TAKANORI , FUNABASHI TSUNEO , YAMAGUCHI NOBORU , IWASAKI KAZUHIKO
IPC分类号： H03M9/00 , G06F3/06 , G06F9/22 , G06F15/16 , G06F15/167 , G06F15/17
摘要： PURPOSE:To attain ease of change in a processing procedure and also to attain high speed real time processing by providing a serial data read control circuit and a serial data write control circuit so as to execute continuously a command. CONSTITUTION:The serial data read control circuit RSC50 consists of a programable logic array PLA30 and an FF8 and the serial data write control circuit WSC60 consists of a PLA17 and an FF16. In starting the RSC50, a main control circuit MC1 issues a serial data processing command to a command register 4 and in starting the WSC60, a write command is issued to a command register 12. When the RSC50 executes the command issued continuously by the MC1 and completes it in this case, the completion is reported to the MC1 and also the WSC60 executes continuously the given command by transmitting a signal to the WSC60. Thus, the change in the processing procedure is attained easily and high speed real time processing is conducted.

47. 发明专利

JPS60107919A PROGRAMMABLE LOGIC ARRAY 失效
公开(公告)号：JPS60107919A
公开(公告)日：1985-06-13
申请号：JP21399283
申请日：1983-11-16
申请人： HITACHI LTD
发明人： YAMAGUCHI NOBORU , SHIMURA TAKANORI , FUNABASHI TSUNEO
IPC分类号： G01R31/28 , H03K19/177
摘要： PURPOSE:To inspect PLA only by generating a pseudo random sequence only once by decreasing the number of output signal lines of the PLA to the number of connectable external terminals by using an exclusive OR circuit. CONSTITUTION:A multiplexer 3 inputs an input signal 1 or the signal of a data pattern generating circuit 2 to output a PLA output 7 through an AND array 4 and an OR array 5 and this is a signal 9 to be connected to an external terminal so as to make a check through an exclusive OR circuit array 8. Consequently, there is no decrease in detection rate even when the number of lines is decreased at the exclusive OR circuit 8 on condition that product term lines 6 which are 1 at the same time are not inputted to two NOR circuits of the OR array 5, that the two NOR circuits each have at least different product term line 6, and that the two NOR circuits have at least one product term line.

48. 发明专利

JPH11191611A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11191611A
公开(公告)日：1999-07-13
申请号：JP35927197
申请日：1997-12-26
申请人： HITACHI LTD
发明人： MIZUNO HIROYUKI , ISHIBASHI KOICHIRO , SHIMURA TAKANORI , HATTORI TOSHIHIRO
IPC分类号： G11C11/413 , G11C5/14 , G11C11/408 , H01L21/822 , H01L23/58 , H01L27/02 , H01L27/04 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To facilitate testing of a substrate bias control circuit, while preventing erroneous operation of a CMOS circuit and minimizing increase in circuit area by providing a negative voltage generating circuit in a substrate bias control circuit with an output terminal and arranging a plurality of substrate driving MOS transistors in a main cirucit for controlling the substrate bias. SOLUTION: A semiconductor integrated circuit device comprises a substrate bias control circuit VBC for controlling the voltage which is applied to the substrate of a transistor, and a stand-by control circuit VBCC for controlling the circuit VBC for making a switching between an active state, where a large quantity of subthreshold leakage current flows through a main circuit comprising transistors and a stand-by state where subthreshold leak current is low. Furthermore, the substrate bias control circuit VBC incorporates a negative voltage generating circuit and has a terminal for outputting a negative voltage generated therefrom to the outside of the device. A gate potential of an least more than one substrate drive MOS transistor is controlled by the substrate bias control circuit VBC.

49. 发明专利

JPH09289471A RADIO COMMUNICATION CARD 失效
公开(公告)号：JPH09289471A
公开(公告)日：1997-11-04
申请号：JP10089196
申请日：1996-04-23
申请人： HITACHI LTD
发明人： TOYODA MITSURU , SHIMURA TAKANORI , KUBO EIJI
IPC分类号： G06F1/16 , G06F3/00 , G06F13/00 , H04B1/38 , H04B1/69 , H04B1/707
摘要： PROBLEM TO BE SOLVED: To provide a radio communication card which can be loaded into a personal computer or a portable information terminal card slot and can attain its miniaturization and small power consumption together with elimination of radiation noises, etc., by packaging a card interface and a base band signal processor into the card in the form of two LSIs. SOLUTION: A card interface circuit 24 of PCMCIA included in a radio communication card 300 secures an interface to a personal computer. A MODEM circuit 22 modulates and demodulates the digital signal. A spectrum spread circuit 21 performs the spectrum spread of the modulated signal and adversely spreads the received signal. A frequency conversion circuit 20 converts a base band signal into the frequency of an RF band. The circuits 24, 22 and 21 is compared of digital circuits and can be turned into a digital LSI, and the circuit 20 consists of an analog circuit of high frequency and can be turned into an analog LSI respectively.

50. 发明专利

JPH08195887A ENCODER FOR STILL PICTURE 失效
公开(公告)号：JPH08195887A
公开(公告)日：1996-07-30
申请号：JP617895
申请日：1995-01-19
申请人： HITACHI LTD
发明人： MORISHIMA KENTA , TAKIZAWA MASAAKI , SHIMURA TAKANORI
IPC分类号： H04N19/60 , G06T9/00 , H03M7/30 , H03M7/40 , H04N1/41 , H04N19/426 , H04N19/625 , H04N19/91 , H04N7/30
摘要： PURPOSE: To provide an inexpensive encoder capable of quickly obtaining a code word and a code length by providing a table compressing and storing the code length and the code word and a means for reading table data and developing them to the code length and the code word. CONSTITUTION: Input picture signals are frequency decomposed in a descrete cosine transformation(DCT) processing block 10 and the respective coefficients are quantized in a quantization processing block 20. Then, the quantized respective coefficients are variable length encoded in a Huffman encoding processing block 30. Then, the category RS of the coefficient to be encoded is obtained in an encoding coefficient category decision processing 31 and code word data are obtained from a corresponding table in a table retrieval processing 32. Further, in a variable length encoding processing 33, the table is developed and the code length and the code word are obtained. In a table development processing 34, by the obtained code length and code word, by performing variable length encoding, Huffman encoding is realized.

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