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41. 发明专利

JPH10145374A SYSTEM SWITCHING METHOD FOR PACKET CONNECTION AND ASYNCHRONOUS TRANSFERRING MODE COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPH10145374A
公开(公告)日：1998-05-29
申请号：JP29841896
申请日：1996-11-11
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SAKAMOTO KENICHI , MIYAGI MORIHITO , TAKATORI MASAHIRO , OTA HIROSHI , TOKURA NOBUYUKI , TATSUNO HIDEO , KAJIYAMA YOSHIO
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/707 , H04L12/709 , H04L12/711 , H04L12/741 , H04L12/801 , H04L12/911 , H04Q11/04
摘要： PROBLEM TO BE SOLVED: To simplify and accelerate switching by allowing a lin card on an output side to mix cells incoming from working connection and protection connection in a receiving-side asynchronous transferring mode ATM device of 1:1 redundancy constitution, so as to execute connection switch by switching only the transmission side. SOLUTION: When setting connection at the time of communicating from an ATM communication equipment 1-1 in the direction of 1-2, a receiving-side ATM communication device 1-2 sets a header conversion table 11 to send a cell by adding the same transmission headers to both of a line card 2 housing working connection and a line card 3 housing protection connection. Thereby cells incoming from both systems are mixed at a line card 1. Consequently, when the receiving side switches an active system from working to protection, the receiving system instantly transfers the cell from the line card 3 of protection to the line card 1.

42. 发明专利

JPH08331142A VIRTUAL PATH SWITCHING SYSTEM 失效
公开(公告)号：JPH08331142A
公开(公告)日：1996-12-13
申请号：JP13531495
申请日：1995-06-01
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD
发明人： KOYANAGI TOSHINORI , IGUCHI KAZUO , OTA HIROSHI , UEMATSU HITOSHI , UEDA HIROMI , ASHI MASAHIRO , NAKANO YUKIO , TAKATORI MASAHIRO
IPC分类号： H04L1/22 , H04L7/00 , H04L12/28 , H04L12/70 , H04L12/709 , H04L12/713 , H04Q3/00
摘要： PURPOSE: To perform switching from a current virtual path to a standby virtual path. CONSTITUTION: A cell for switching is inserted to the same positions of the current virtual path and the standby virtual path by a transmitter 20, and a cell for switching control on either side of the current virtual path or the standby virtual path is detected by a receiver 30. The cell on one side is stored in a phase absorption buffer 48, and the cell for switching control on the path on the other side is detected, and the cell string of the current virtual path is switched to the one of the standby path read out or transmitted from the phase absorption buffer 48.

43. 发明专利

JPH08328871A PARALLEL PROCESSING PROGRAM GENERATION AND EXECUTION METHODS AND EXECUTION DEVICE OF THESE METHODS 失效
公开(公告)号：JPH08328871A
公开(公告)日：1996-12-13
申请号：JP13308295
申请日：1995-05-31
申请人： HITACHI LTD
发明人： OTA HIROSHI
IPC分类号： G06F15/16 , G06F9/45
摘要： PURPOSE: To turn the sentences used for the sequential input and output into the parallel sentences and to generate a parallel processing program with no deterioration of portability nor user's correction by retrieving the input/output sentences used for the sequential input an output and converting these retrieved sentences into the input/output sentences used for the parallel input and output. CONSTITUTION: A syntax analysis part 60 of a parallel compiler 6 reads a parallel program 50 and retrieves the I/O(input/output) sentences, etc., to generate an intermediate language 54. An I/O sentence parallel part 61 turns the I/O sentences of the non-parallel program 50 into the parallel sentences. Then a code generation part 63 reads the language 54 to generate a program 51. In such a constitution, the I/O sentences of a sequential processing program, are retrieved and a code is added to decide weather the file of I/O sentences is used for the parallel or sequential input and output. Based on this decision result, the parallel or sequential input and output are carried out. Furthermore, another code is added to perform the conversion according to the distribution shape of the I/O processing data.

44. 发明专利

JPH08319982A TWO-STAGE UNLUBRICATED SCREW COMPRESSOR 失效
公开(公告)号：JPH08319982A
公开(公告)日：1996-12-03
申请号：JP12622195
申请日：1995-05-25
申请人： HITACHI LTD
发明人： OTA HIROSHI , NISHIMURA HITOSHI , SASAKI RYOJI , OSADA YOSHIRO
IPC分类号： F04C18/16 , F04C28/02 , F04C28/06 , F04C29/10
摘要： PURPOSE: To feed dry air, containing no drain, to a two-stage compressor and to prevent drain from residing at the two-stage compressor after a stop by a method wherein when the compressor is stopped, after unload operation is forcibly effected for a given time, the compressor is stopped. CONSTITUTION: Compressed air the temperature of which is increased in such a way to be boosted by a one-stag compressor 1 is cooled by a cooler 3 (an intercooler). After the compressed air is compressed to a given pressure by a two-stage compressor body 2, it is discharged through a cooler 4 (a high precooler), a check valve 9, and a cooler 5 (an after-cooler). In which case, when an amount of using air is decreased and a pressure in a delivery piping is increased to a value higher than a given pressure, the increased pressure is detected by a pressure switch 10 to switch two three-way solenoid valves 12 and 13, a chamber A is pressurized, and an intake air throttle valve 6 is closed. Further, simultaneously, a gas release valve 7 is opened, and air in a delivery piping running between a compressor body and the check valve 9 is released (unloaded). After unload operation is performed for a given time, the compressor is stopped.

45. 发明专利

JPH08213985A VIRTUAL PATH SWITCHING CONTROL METHOD FOR ATM NETWORK 失效
公开(公告)号：JPH08213985A
公开(公告)日：1996-08-20
申请号：JP1567895
申请日：1995-02-02
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKATORI MASAHIRO , NAKANO YUKIO , ASHI MASAHIRO , UEDA HIROMI , UEMATSU HITOSHI , OTA HIROSHI
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/70 , H04L12/707 , H04L12/709 , H04L12/801 , H04L12/911
摘要： PURPOSE: To reduce an influence upon the other traffics and to quickly switch plural virtual path(VP) by generating a switching control OAM cell with a long period in the case of the absence of a switching request and generating it with a short period in the case of the presence of the switching request. CONSTITUTION: The switching control OAM cell is generated with a long period T1 at the time of the absence of the switching request in a node (normally), and a period T2 of switching request generation is made shorter than this period T1. Thus, the switching control OAM cell is used to ensure the coincidence between current paths of two transmission and reception leads even if another information cell or the like doesn't exist. Further, current system/ standby system VP switching control is quickly performed at the time of the presence of the switching request. The period of OAM cell generation is varied in this manner to reduce the influence upon traffics.

46. 发明专利

JPH07219909A METHOD FOR CONVERTING PROGRAM 失效
公开(公告)号：JPH07219909A
公开(公告)日：1995-08-18
申请号：JP1119694
申请日：1994-02-02
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： OTA HIROSHI , SAITO TETSURO , SAITO YASUHIKO , UMINAGA MASAHIRO
IPC分类号： G06F15/16 , G06F9/45
摘要： PURPOSE:To evade the generation of an error due to mismatch between the array areas of plural procedures which is generated when the contents of a sequentially processing program are arrayed in parallel in each procedure. CONSTITUTION:An array to be referred to in each procedure is analyzed (101), the division size of the array is determined (102) and the area size of an array element to be referred in a procedure concerned except an area specified by the division size is specified (103). Whether the range of an array area secured for the initial execution sentence of each procedure and a succeeding execution sentence to be a slave procedure accessing sentence coincides with the array element reference area of the procedure itself or not is decided, and when both the areas are mismatched, a library function accessing sentence for rescuing the areas of the array so that the secured array area matches with the array element reference range of its own procedure is added.

47. 发明专利

JPH06301721A WHOLE SENTENCE DATA BASE RETRIEVING METHOD 失效
公开(公告)号：JPH06301721A
公开(公告)日：1994-10-28
申请号：JP9108093
申请日：1993-04-19
申请人： HITACHI LTD
发明人： OTA HIROSHI , NOMURA YASUTSUGU , KUREBAYASHI TETSUYA , YAMADA KIYOSHI , NEGISHI MASAMITSU , OYAMA KEIZO , MIYAZAWA AKIRA , SHIBANO KOJI
IPC分类号： G06F17/30 , G06F15/40
摘要： PURPOSE:To provide the whole sentence data base retrieving system by which the designation of a retrieval request sentence containing the logical structure information of a document and the display of a result of retrieval can be executed, in the processing for retrieving the whole sentence of the document having a logical structure. CONSTITUTION:An original document described by an inputted SGML is decomposed, based on its structure information, a data base of structure information 7, tag information 8 and text information 9 is generated by a data base generating part 3 of an SGML server, the generated data base is stored in a data base control system, a retrieval request 16 inputted by the SGML is converted to an SQL being data base retrieval language and a retrieval processing is executed by a relational data base control system, and a result of retrieval 15 is organized to an SGML 17, and displayed on a work station.

48. 发明专利

JPH06295288A PRIMARY RECURSIVE OPERATION CALCULATION METHOD ON SUPER-PARALLEL COMPUTER 失效
公开(公告)号：JPH06295288A
公开(公告)日：1994-10-21
申请号：JP8293693
申请日：1993-04-09
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SAITO TETSURO , UMINAGA MASAHIRO , ONO HIROYUKI , NAKAGAWA TOMOHITO , OTA HIROSHI
IPC分类号： G06F9/38 , G06F15/16 , G06F15/173 , G06F15/80 , G06F17/16 , G06F15/347
摘要： PURPOSE:To increase the operation speed and to reduce the congestion of a network by calculating local primary recursive operations and cumulative coefficients in respective nodes of mutually connected networks and totalizing the results while sending them to route nodes and obtaining the final result in the route. CONSTITUTION:A processor in a super-parallel computer receives information 1 and information 2 and executes the operation between information 1 and a variable 1 of the processor and stores the result in the variable 1 and executes the operation between information 2 and a variable 2 of the processor and stores the result in the variable 2. Next, operation 3 among the variable 1, the variable 2, and a variable 3 of the processor is executed and the result is stored in the variable 2, and operation 2 between the variable 2 and a variable 4 of the processor is executed and the result is stored in the variable 2. Further, the processor receives information 1 and information 2 and executes operation 3 among the variable 1, information 1, and information 2 and stores the result in the variable 1 and executes operation 2 between the variable 2 and information 2 and stores the result in the variable 2 and transmits contents of the variable 1 and the variable 2 to a preliminarily determined processor.

49. 发明专利

JPH05292118A 失效
公开(公告)号：JPH05292118A
公开(公告)日：1993-11-05
申请号：JP9468292
申请日：1992-04-15
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP , HITACHI LTD
发明人： TANIGUCHI IKUO , HANAOKA SUSUMU , OTA HIROSHI , UEDA HIROMI , KURANO TAKANORI , NISHIHARA MOTOO , ASHI MASAHIRO , NAKANO YUKIO
IPC分类号： H03M13/00 , H04L12/24 , H04L12/26 , H04L12/48
摘要： PURPOSE:To reduce the scale of the circuit and to decrease a delay in a line with respect to the transmission quality supervisory system in the transmitter/ receiver and communication system for the communication employing the ATM system. CONSTITUTION:A transmitter 310 is configured such that when a user cell number reaches a required number and an idle cell detection section 220 detects an idle cell, an output section 105 inserts the result from the calculation for error supervision for each transmission path (VP) at a transmission arithmetic operation section 100 to an idle cell based on a control signal outputted from a cell number variable control section 250 and sends the result as a supervisory OAM cell. Furthermore, a receiver 320 uses an error discrimination section 200 to compare the result obtained by the arithmetic operation for error supervision as to a block separated by an OAM cell received by a reception arithmetic operation section 110 with the result of arithmetic operation extracted from the OAM cell received by a reception information extract section 180 thereby implementing error supervision to a cell string of variable length.

50. 发明专利

JPH04257928A METHOD AND DEVICE FOR ALLOCATING PROCESSOR IN PARALLEL COMPUTER AND COMPILER 失效
公开(公告)号：JPH04257928A
公开(公告)日：1992-09-14
申请号：JP1974991
申请日：1991-02-13
申请人： HITACHI LTD , HITACHI MICRO SYSTEM KK , HITACHI NUCLEAR ENG
发明人： OTA HIROSHI , SAKOTA KOUSUKE , SAITO TETSURO , MAEDA EIICHIRO , YAMAMOTO TOSHIYUKI
IPC分类号： G06F9/44 , G06F9/45 , G06F15/16 , G06F15/177
摘要： PURPOSE:To minimize the number of times for transferring data by deciding an candidata processor to be allocated to the operation of an internal node while tracing a tree by bottom-up, and next deciding a processor while tracing it by top-down. CONSTITUTION:An expression is expressed in the form of the tree having data as a leaf node and an operator as an internal node. Then, each node of the three is traced by bottom-up 10, and the set of candidates [candidata processor (PE)] for the PE to be allocated to the operation of the internal node is decided 100. Next, each node of the tree is traced by top-down 11, the PE to be allocated to the operation of the internal node is decided 110, and the PE is allocated to the operation.

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