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    • 50. 发明专利
    • MANUFACTURE OF MULTI-LAYER PRINTED WIRING BOARD
    • JPH10163629A
    • 1998-06-19
    • JP31836596
    • 1996-11-28
    • HITACHI CHEMICAL CO LTD
    • FUKAI HIROYUKIHAMA MASAYUKITAKANEZAWA SHIN
    • H05K3/46
    • PROBLEM TO BE SOLVED: To omit a plating pretreatment, by forming a multi-layer by repeating such process as a via hole is formed on an insulation layer comprising a plating catalyser on an insulation substrate where the first circuit layer is already formed and then copper is plated on the surface of insulation layer and on the inside wall of via hole, in this order. SOLUTION: An insulation layer 3 comprising a plating catalyst is formed (b) on an insulation substrate 2 where the first circuit layer 1 is already formed (a), and a via hole 4 for connecting the first circuit layer 1 and the second circuit layer 5 together is formed on an insulation layer 3 (c). The second circuit layer 5 is formed in the same manner as the first circuit layer 1 (e), to provide a 3-layer printed wiring board comprising a power source layer and/or a ground layer G, the first circuit layer 1, and the second circuit layer 5. For further multiplication in layers, processes starting with formation of insulation layer, (b)-(e), are repeated. As a result, a plating pretreatment can be omitted, thus the cost for multi-layer printed wiring boards by build-up method is significantly reduced.