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41. 发明专利

JPS5936934A Glass passivation method 失效
标题翻译：玻璃钝化方法
公开(公告)号：JPS5936934A
公开(公告)日：1984-02-29
申请号：JP14732882
申请日：1982-08-25
申请人： Fuji Electric Co Ltd
发明人： WADA KAZUHISA
IPC分类号： H01L21/316
CPC分类号： H01L21/316
摘要： PURPOSE:To form a surface protection layer having a high maximum allowable junction temperature and excellent resistivity to chemicals by depositing a glass layer of ZnO system on the exposed part of P-N junction by electrolysis, depositing the glass layer of PbO base thereon also by electrolysis and then baking these glass layers. CONSTITUTION:The ZnO glass and PbO glass having almost the same baking condition and grain size of 3-5mum are prepared in the individual electrolysis reservoirs. After the diode wafer 1 of which P-N junction is exposed through the groove 2 is pre-processed by boiled nitric acid, the layer 4 is deposited by the electrolysis in the thickness of 15-20mum in the electrolysis reservoir for the ZnO glass and then the layer 5 is deposited by the electrolysis in the thickness of 10-15mum in the electrolysis reservoir for the PbO glass. The silicon wafers having completed deposition by electrolysis are arranged on the quartz slit and these are subjected to the heat processing under the specified heat processing condition. A protection film having a high maximum allowable junction temperature and resistivity to chemicals owing to the characteristics of both glass materials can be formed.
摘要翻译：目的：通过电解在PN结的暴露部分上沉积ZnO系玻璃层，形成具有高最大允许结温和优异电阻率的表面保护层，还可通过电解沉积PbO基底玻璃层，然后烘烤这些玻璃层。构成：在各个电解槽中制备具有几乎相同烘烤条件和3-5μm的粒径的ZnO玻璃和PbO玻璃。在通过凹槽2暴露PN结的二极管晶片1之后，通过煮沸的硝酸进行预处理，在ZnO玻璃的电解槽中通过电解15-20μm的电解沉积层4，在用于PbO玻璃的电解槽中，通过电解沉积厚度为10-15μm的层5。通过电解完成沉积的硅晶片布置在石英狭缝上，并在规定的热处理条件下进行热处理。可以形成由于两种玻璃材料的特性而具有高的最大允许结温和对化学品的电阻率的保护膜。

42. 发明专利

JPS5916376A Bidirectional thyristor 失效
标题翻译：双向THYRISTOR
公开(公告)号：JPS5916376A
公开(公告)日：1984-01-27
申请号：JP12544182
申请日：1982-07-19
申请人： Fuji Electric Co Ltd
发明人： WADA KAZUHISA
IPC分类号： H01L29/74 , H01L29/747
CPC分类号： H01L29/747
摘要： PURPOSE:To obtain the triac having excellent commutation characteristics by a method wherein the surface of the boundary part of two thyristor regions is coated with an insulating layer, and the main electrode is provided in such a manner that it is covering respectively the surfaces of the insulating layer and both exposed regions located on both sides of a semiconductor substrate. CONSTITUTION:In a silicon plate 1, a thyristor region 11 consisting of four-layer structure of n1p1n2p2 and another thyristor region 12 consisting of four-layer structure of p1n2p2n3 are provided adjoiningly facing inverse directions each other. The boundary parts of the n-emitter layer n1 of the thyristor region 11 exposed on the under side of a silicon plate 7, the p-emitter layer p1 of the thyristor region 12, the n-emitter layer n3 of the thyristor region 12 exposed on the upper surface, and the p-emitter layer p2 of the thyristor region are covered by the insulating layer 2 consisting of an oxide film. On the above insulating layer 2 and on the surface of the silicon plate 1 where the insulating film is not covered, metal layers 3, 4 and 5 are provided by performing a vapor-deposition, for example. Main electrode terminals A1 and A2 are connected to the metal layers 3 and 5, and a gate terminal G is connected to the metal layer 4.
摘要翻译：目的：为了获得具有优异的换向特性的三端双向可控硅开关元件，其中两个晶闸管区域的边界部分的表面涂覆有绝缘层，并且主电极设置成分别覆盖绝缘层和位于半导体衬底两侧的两个暴露区域。构成：在硅板1中，由n1p1n2p2的四层结构构成的晶闸管区域11和由p1n2p2n3的四层结构构成的另一个可控硅区域12彼此相反地设置。暴露在硅板7的下侧的晶闸管区域11的n发射极层n1的边界部分，晶闸管区域12的p型发射极层p1，可控硅区域12的n极发射极层n3露出晶闸管区域的p型发射极层p2由氧化膜构成的绝缘层2覆盖。在上述绝缘层2上和绝缘膜未被覆盖的硅板1的表面上，例如通过进行气相沉积来提供金属层3,4和5。主电极端子A1和A2连接到金属层3和5，栅极端子G连接到金属层4。

43. 发明专利

JPS58157167A MANUFACTURE OF THYRISTOR 失效
公开(公告)号：JPS58157167A
公开(公告)日：1983-09-19
申请号：JP4035982
申请日：1982-03-15
申请人： FUJI ELECTRIC CO LTD
发明人： WADA KAZUHISA
IPC分类号： H01L29/73 , H01L21/331 , H01L29/06 , H01L29/74
摘要： PURPOSE:To make leakage currents forward and reverse small and the gate ignition characteristic better, with less decrease of forward withstand voltage, by forming a bevel structure which becomes a negative bevel to the P-N junction between both P-N base layers. CONSTITUTION:When N-emitter regions 12 are formed by P diffusion after providing a mask 13 of an oxide film on the surface of an Si substrate 1, simultaneously additional N regions 14 surrounding the regions 12 via a clearance are formed. A mask 2 of a photo resist film is provided so that the outer periphery is positioned on the part between this N region 12 and N region 14, and the mask 2 is provided also on the area on the back surface opposed of the Si substrate 1. When grooves 3 are formed by etching, the N regions 14 are removed by this etching. When the substrate is divided at the position of dot lines 4, the bevel surface 15 and the exposed part of P-N junction of the surface are covered with a passivation film 5, and a cathode electrode 6, a gate electrode 7, and an anode electrode 8 are adhered on each region which is exposed, a thyristor element can be obtained.

44. 发明专利

JPS5688375A SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPS5688375A
公开(公告)日：1981-07-17
申请号：JP16618579
申请日：1979-12-20
申请人： FUJI ELECTRIC CO LTD
发明人： WADA KAZUHISA
IPC分类号： H01L29/861 , H01L23/492
摘要： PURPOSE:To facilitate the cooperation for connecting elements of reverse polarity by bonding an electrode having small area through an intermediate electrode to a container substrate when fixing the semiconductor elements having electrodes formed on the entire one surface and electrodes having limited area formed on the other surface to the container substrate. CONSTITUTION:An N type layer is formed on one surface of an N type Si substrate, a P type region is diffused on the other surface, an entire surface electrode is formed on the N type layer of one surface, an electrode having area corresponding to the area of the P type region is formed on the other surface, and a diode of N - N-P architecture is thus formed. When a circuit is formed by using planar diode pair having asymmetrical electrfodes on both front and back surfaces, if the container substrate 3 is secured directly on the respective surfaces, the cooperation of the circuit can be disabled. Accordingly, a Cu intermediate electrode 4 having smaller area than the electrode of a reverse polarity diode is disposed through solder 5 on the small area electrode side of the diode, so that the cooperation of the paired diodes can be obtained.

45. 发明专利

JPS5618461A PLANAR TYPE SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPS5618461A
公开(公告)日：1981-02-21
申请号：JP9454579
申请日：1979-07-25
申请人： FUJI ELECTRIC CO LTD
发明人： WADA KAZUHISA
IPC分类号： H01L29/73 , H01L21/331 , H01L29/06 , H01L29/861
摘要： PURPOSE:To independently adjust the forward voltage drop and reverse voltage stopping capacity in a planar type semiconductor element by forming one of two adjacent layers interposed at a P-N junction of one surface region having low impurity density and an internal region having high impurity density. CONSTITUTION:In case of a planar type diode, a forward voltage drop is mainly affected by the impurity density of the internal region 11 of an N-type layer existed in a direction for connecting both electrodes 6 and 7, while a reverse voltage stopping capacity depends mainly upon the impurity density of the surface region 12 of the N-type layer making contact with the P-N junction 8. The impurity densities of the two regions 11, 12 are separately set, the region 11 is set in high impurity density, and the region 12 is set in low impurity density.

46. 发明专利

JPS55162264A MANUFACTURE OF HIGHHSPEED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS55162264A
公开(公告)日：1980-12-17
申请号：JP6969779
申请日：1979-06-04
申请人： FUJI ELECTRIC CO LTD
发明人： OKAZAKI TATSUROU , WADA KAZUHISA
IPC分类号： H01L29/73 , H01L21/316 , H01L21/331 , H01L29/167 , H01L29/74 , H01L29/861
摘要： PURPOSE:To form electrodes with high precision and obtain a high-speed semiconductor device by the method wherein the diffusion of a lifetime killer and the formation of a glass protective film are operated by a skillfull combination of heat- oxidation and low-temperature-oxidation films. CONSTITUTION:A p layer and an n layer are formed on an n-type Si substrate. Heat-oxidation film 4 is formed on its surface, and oxide film 4 on the surface of p base layer 11 and on the surface of n emitter layer 31 is removed; an Au is diffused. Next, all oxide film 4 is removed, and thin low-temperature-oxidation film 5 is formed newly. Oxide film 5 is opened at the surface of xposure of the junction of n layer 2 and p layer 1. The opening is fitted with glass 6 by electrophoresis and sintered. Since it is not exposed to high temperature in electrophoresis, the low- temperature-oxidation film functions as a mask sufficiently. When oxide film 5 is photoetched, a window can be open with high precision, unlike glass film. Then, electrodes 7-9 are fitted, and the process is completed.

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