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41. 发明专利

JPS5821942A DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPS5821942A
公开(公告)日：1983-02-09
申请号：JP11906681
申请日：1981-07-31
申请人： HITACHI LTD
发明人： HIYAMA KUNIO , KAWAKITA KENJI , TAKADA OSAMU
摘要： PURPOSE:To increase the efficiency for data communication, by detecting coincidence between the channel number of information during the reception and the channel number stored in a storage device and then starting a circuit which controls the packet communication or the circuit exchange in accordance with the packet communication control. CONSTITUTION:The connection controlling packet transmitted to a loop transmission line 1200 is received at each node device and then sent to a packet controlling part 700 from a packet controlling part 400. Coincidence is checked at the part 700 between the address of the destination and the own address. If the coincidence is obtained, a link controlling part 600 is started. Then the data is fetched into the part 600. In the case of an exchange of packets, the head channel of the packet is detected from the channel number signal through a packet interface part 1100 for the node device of the receiving side, and then the part 700 is started. Thus the data communication is possible for the circuits of both the circuit exchanging system and the packet exchanging system.

42. 发明专利

JPS5821941A DATA COMMUNICATION SYSTEM 失效
公开(公告)号：JPS5821941A
公开(公告)日：1983-02-09
申请号：JP11906581
申请日：1981-07-31
申请人： HITACHI LTD
发明人： HIYAMA KUNIO , KAWAKITA KENJI , TAKADA OSAMU
IPC分类号： H04L12/43
摘要： PURPOSE:To perform the communication of data in time division between terminal devices, by adding a connection controlling code showing the transmission request and the discrimination of the end request of a node device at the remote side and the circuit exchanging code showing the channel number to the region of the connection controlling information. CONSTITUTION:Plural communicaton node devices 2 are connected to a common signal transmission line 1. At least one of these devices 2 produces repetitively plural channels in a certain period to transmit them. Each device 2 performs the communication of data through a channel. Then plural continuous channels are used as the regions to transmit the connection controlling information. The information region has a frame constitution which can use both a circuit exchange and a packet exchange together and includes a synchronizing region X, the connection control code showing the discrimination between the transmission request and the end request of the address data of the device 2 and the circuit exchange code showing the channel number.

43. 发明专利

JPS5559536A BUS PRIORITY CONTROL SYSTEM IN LOOP BUS NETWORK SYSTEM 失效
公开(公告)号：JPS5559536A
公开(公告)日：1980-05-06
申请号：JP13265678
申请日：1978-10-30
申请人： HITACHI LTD
发明人： HATADA MINORU , HIYAMA KUNIO , IHARA KOUICHI , KUMA HISAO
IPC分类号： G06F13/00 , G06F13/374 , G06F15/16 , G06F15/173 , G06F15/177 , H04L12/433
摘要： PURPOSE:To realize a loop bus priority control system which requires no special control unit on the loop by transmitting the bus control data including the priority level No. of the message plus the priority No. allotted to each host. CONSTITUTION:The bus control data is formed by providing the subpriority No. decided by the host as well as the level No. of the priority as shown in Fig. (a) to the message which is transmitted through each host processor 1. In case the messages of levels 2, 2 and 1 are produced at hosts I, IV and VIII each, the priority data produced at node processor 2 connected to each host turn to 23, 28 and 13 respectively to be transmitted in the form of the bus control data. Each node compared the data received from the preceding step node with the data transmitted from the node itself, and sends the received data to the next step only when the received data is higher in the priority than its own data. Otherwise the received data is disused. As a result, only data 28 generated at host IV has one circulation along the loop bus and then returns to host IV to acquire the using right for the bus.

44. 发明专利

JPS5429943A COMPOSITE DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS5429943A
公开(公告)日：1979-03-06
申请号：JP9504277
申请日：1977-08-10
申请人： HITACHI LTD
发明人： KITANI YUUICHI , HIYAMA KUNIO , SHIYOUDA AKIO , SUZUKI TAHEI , TOKITA YOSHIAKI
IPC分类号： G06F15/16 , G06F1/12 , G06F15/177
摘要： PURPOSE:To reduce the queuing time by giving the timer interruption to each data processing unit, which constitutes the composite data processing system, while shifting the timing.

45. 发明专利

JPS52135641A DEBUGGING MEANS FOR MICRO PROGRAM 失效
公开(公告)号：JPS52135641A
公开(公告)日：1977-11-12
申请号：JP5222276
申请日：1976-05-10
申请人： HITACHI LTD
发明人： MIZUHARA NOBORU , HIYAMA KUNIO
IPC分类号： G06F11/28 , G06F9/00 , G06F11/00
摘要： PURPOSE:To increase the productivity of micro program as the debugging means for micro program, so that arbitrary machine language instruction series or the carrier of various registers in executing the micro instruction series are in storage.

46. 发明专利

JPS52126137A MEMORY REFERENCE CAREER RECORDING SYSTEM OF DATA PROCESSING UNIT 失效
公开(公告)号：JPS52126137A
公开(公告)日：1977-10-22
申请号：JP4244576
申请日：1976-04-16
申请人： HITACHI LTD
发明人： HIYAMA KUNIO
IPC分类号： G06F12/12 , G11C8/00
摘要： PURPOSE:To improve accuracy of selecting unnecessary page, and shorten the time of selecting process and further, obtain number of pages accurately within a short time, thus eliminate unavailing page transfer operation as a whole system, by providing plural number of reference digit for each page.

47. 发明专利

JPH0360242A NETWORK SYSTEM 失效
公开(公告)号：JPH0360242A
公开(公告)日：1991-03-15
申请号：JP19410589
申请日：1989-07-28
申请人： HITACHI LTD
发明人： TAKAHASHI YASUHIRO , TSUKAGOSHI MASAHITO , TERADA MATSUAKI , HASHIMOTO TOYOKAZU , HIYAMA KUNIO
IPC分类号： H04L12/42
摘要： PURPOSE:To improve the data transfer capacity of a whole system by providing each node with a function to receive data from one highway in principle and transmit and receive the data to/from all the highways only in the case for a common data area. CONSTITUTION:A network system consists of a trunk line node 300, a trunk line LAN 301, a branch line LAN 303, and terminal equipment 304. Then, each node device 300 on a loop network executes reception processing operation for a communication frame inputted from one specified communication channel among plural communication channels (highway) multiplexed physically or logically, and executes transmission processing operation by using the communication frame flowing in the optional communication channel selected correspondingly to a destination node. Thus, the data transfer capacity of the whole system can be improved without accelerating information processing speed at each node device 300.

48. 发明专利

JPS60203039A LOOP-SHAPED NETWORK FORMATION SYSTEM 失效
公开(公告)号：JPS60203039A
公开(公告)日：1985-10-14
申请号：JP5824884
申请日：1984-03-28
申请人： HITACHI LTD
发明人： KAWAKITA KENJI , HIYAMA KUNIO
IPC分类号： H04L12/437
摘要： PURPOSE:To improve both working efficiency and maintenance performance with a loop-shaped network by replacing a faulty area without affecting the transmission system of a loop-back state in case >=2 faults occur at a time in different transmission systems. CONSTITUTION:A repeater part 131 consists of a transmission part 141 led to a transmission line 101 of operation system and a reception part 151 led from a transmission line 102 of spare system. While another repeater part 132 consists of a reception part 152 for the line 101 and a transmission part 142 for the line 102. In case >=2 faults occur at a time in two different transmission systems, the parts 134 and 137 including the faulty areas can be replaced with others since they form no loop-back state.

49. 发明专利

JPS6012837A DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JPS6012837A
公开(公告)日：1985-01-23
申请号：JP12118683
申请日：1983-07-04
申请人： HITACHI LTD
发明人： HOSHI TOORU , SUZUKI MICHIO , TAKENOUCHI HIROO , KONASE TOSHIAKI , HIYAMA KUNIO
IPC分类号： H04L29/10 , H04L12/00 , H04L13/00 , H04L11/02
摘要： PURPOSE:To reduce the number of signal lines between a data terminal and a data switching network by synthesizing plural pairs of signal lines and then separating these signal lines again in the interface between the data terminal and data switching network. CONSTITUTION:A transmission data line T and a control line C from a terminal 1 having an X.21 interface are combined to a T' line in an interface device 3, then separated into respective information of the T line and C line of the X.21 interface again by an interface device 4 in a network terminating device 2. On the other hand, a receiving data line R to the terminal 1, an indication line I and a signal element clock line S are synthesized to an R' line by the device 4 in the device 2, separated again in the device 3 and then transmitted to the terminal 1. Therefore, the devices 3 and 2 are satisfactorily connected only by connecting the two pairs of signals lines T', R', and if the device 3 and the terminal 1 are arranged adjacently, the section connecting the five pairs of signal lines T, R, C, I and S requires no long distance.

50. 发明专利

JPS59231943A DEVICE FOR PREVENTING DISABLED COMMUNICATION 失效
公开(公告)号：JPS59231943A
公开(公告)日：1984-12-26
申请号：JP10585583
申请日：1983-06-15
申请人： HITACHI LTD
发明人： TAKAHASHI YASUHIRO , KAWAKITA KENJI , HIYAMA KUNIO
IPC分类号： H04L5/22 , H04L12/26 , H04L11/00 , H04J3/00
摘要： PURPOSE:To prevent disabled communication by detecting the erroneous occupancy of a packet region depending on the relation between the continuous passing number of time of an occupied packed region passing through the own node and the number of nodes connected in a loop network, to release the region. CONSTITUTION:A detecting circuit 31 supervises always whether a packet region of a frame passing through a node device is in operation or idle, every time the packet in operation passes, a signal (a) is applied to a counter 32 so as to increment it. When an dile packet is incoming, a signal (b) is applied to the counter 32 so as to reset it. When a comparator circuit 33 recognizes that the value of the counter exceeds the node number connected to a loop, the circuit 33 discriminates that the information of ''in operation/idle'' is rewritten because of an error like a fault, s signal is given to a clear circuit of packet region operating information, the information is rewritten into packet region ''idle'' and the packet region is restored to give a packet operating right to a node at the downstream.

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