专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

JPH0215404A RECORDING ERROR RETRYING METHOD FOR RECORDING DEVICE 失效
公开(公告)号：JPH0215404A
公开(公告)日：1990-01-19
申请号：JP16636388
申请日：1988-07-04
申请人： FUJITSU LTD
发明人： TANIYAMA YUKIO
IPC分类号： G11B5/09 , G11B20/18
摘要： PURPOSE:To effectively use a recording medium by error-retrying in units of block. CONSTITUTION:Data blocks 2, 3,... are recorded in units of the block on a recording medium 1. When the recorded data are checked, and they are detected to be recording errors, the same data are recoded on the position where the block has been recorded, the recording error retrying is executed without shifting the recording block, and the recording medium can be effectively used.

42. 发明专利

JPS62134802A READ BLOCK CONTROL SYSTEM 失效
公开(公告)号：JPS62134802A
公开(公告)日：1987-06-17
申请号：JP27374785
申请日：1985-12-05
申请人： FUJITSU LTD
发明人： OBA YOSHIFUMI , TANIYAMA YUKIO
IPC分类号： G11B20/10 , G11B5/09 , G11B15/02 , G11B15/087
摘要： PURPOSE:To shorten the processing time by starting volume reading through the information of load completion and transferring contents stored in a buffer according to a read instruction. CONSTITUTION:When the load completion of the prescribed block which is loaded on a magnetic tape device 10 with the commitment of an operator is reported, a magnetic tap controller 1 demodulates 4 data read through a tape 12 from a read head 13 under the control of a controller 2, and stores it in the buffer 3. Simultaneously a drive control part 15 is controlled to rewind the tape 12 to a start tip. According to a read instruction from a host device OS the contents in the buffer 3 are instantaneously transferred to the device OS, while according to a write instruction the contents in the buffer 3 is read out and modulated 5, and written on the tape 12 returning to the start tip by a write head 14. Thus the processing time can be shortened by the time reading the volume.

43. 发明专利

JPS6192474A Control system of magnetic tape device 失效
标题翻译：磁带设备控制系统
公开(公告)号：JPS6192474A
公开(公告)日：1986-05-10
申请号：JP21449484
申请日：1984-10-13
申请人： Fujitsu Ltd
发明人： TANIYAMA YUKIO , HAYAKAWA AKIHIRO , TAKAHASHI YOICHI , TANAKA HIDEHIKO , OBA YOSHIFUMI
IPC分类号： G11B20/10
CPC分类号： G11B20/10
摘要： PURPOSE:To ensure the continuity of BLOCK-ID even after passing for a tape mark by providing a register storing a control plug to a magnetic tape unit, turning on the control plug when a block without block identification number is accessed to change a block access method. CONSTITUTION:A magnetic tape unit 10 is provided with a control flag storage register CFR and the register is provided with the control flag U bit. The control flag U bit is set when a tape mark is detected and when it is set, a value of a register BIDR is incredible but a file serial number FSN is credible. When the U bit is set, the process proceeds the next block in the presence of back space, the ID of the next block is read to discriminate that the BLOCK-ID is correct (without confirming processing of comparison with an expected value), and the value of the register BIDR is renewed to the ID value. Thus, the succeeding process is normal and the continuity of the BLOCK-ID in the register BIDR is ensured.
摘要翻译：目的：为了确保BLOCK-ID的连续性，即使通过提供一个存储控制插头到磁带单元的寄存器来传送磁带标记，当访问没有块标识号的块来打开控制插头，以更改块访问方法。构成：磁带单元10设置有控制标志存储寄存器CFR，并且该寄存器具有控制标志U位。当检测到磁带标记时，控制标志位U被置位，当它被设置时，寄存器BIDR的值是令人难以置信的，但文件序列号FSN是可信的。当U位被置位时，处理在存在后退空间的情况下进行下一个块，读取下一个块的ID以区分BLOCK-ID是正确的（而不确定与期望值的比较处理），以及寄存器BIDR的值被更新为ID值。因此，后续处理是正常的，并且确保了寄存器BIDR中的BLOCK-ID的连续性。

44. 发明专利

JPS60187914A DIAGNOSTIC METHOD OF MAGNETIC HEAD 失效
公开(公告)号：JPS60187914A
公开(公告)日：1985-09-25
申请号：JP4450284
申请日：1984-03-08
申请人： FUJITSU LTD
发明人： TANIYAMA YUKIO , HAYAKAWA AKIHIRO
IPC分类号： G11B5/455 , G11B20/10 , G11B20/24
摘要： PURPOSE:To attain the measurement of crosstalk between adjacent lead heads by detecting an output of lead heads reading a track without any recording while changing the threshold value and transmitting the result to a high-order device. CONSTITUTION:A write start signal is given to a terminal A and a mask data write signal is given to a terminal B at each other track to a write head 4 so as to form a track where all 1 data are written on a magnetic tape 1 and no data is written alternately. The data block is read by a read head 8 and a slice level of a peak detection circuit 11 is set minutely so as to detect the crosstalk from the adjacent read head and its peak value is transmitted from a terminal C to the high-order device. Further, the high-order device detects that it is a peak in reading the data block by using an output of a time sense circuit 12 so as not to make mis-decision when the peak is not detected even with the minimum slice level.

45. 发明专利

JPS59148954A Patrolling system of control storage 失效
标题翻译：控制存储控制系统
公开(公告)号：JPS59148954A
公开(公告)日：1984-08-25
申请号：JP2229683
申请日：1983-02-14
申请人： Fujitsu Ltd
发明人： TANIYAMA YUKIO , TANAKA HIDEHIKO
IPC分类号： G06F9/22 , G06F11/00 , G06F12/16
CPC分类号： G06F11/004
摘要： PURPOSE:To prevent the regeneration of an error by detecting a generated uncorrectable error, storing its address, informing the address and then rewriting data in the address in case of accessing to a control storage for a microprogram. CONSTITUTION:The control storage 2 is read out by an address specified by a register 6 and checked by an ECC circuit 3. When a one-bit error is detected, the corrected data are sent to a register 4, and if uncorrectable 2-bit error is detected, an error detecting circuit 7 opens a gate 8 and stores the address of the generated error of the control storage 2 which is specified by the register 6 in a trace memory 9. When the error signal is sent from the detecting circuit 7, an arithmetic circuit 5 reports the signal to the upper device through a terminal A and starts a loader circuit 1. Then the arithmetic circuit 5 reads out the trace memory 9, informs the address of the generated error to a loader circuit 1 and rewrites the corrected data in the address. Thus, rewriting is attained easily and the regeneration of the error can be prevented.
摘要翻译：目的：通过检测生成的不可校正错误，存储其地址，通知地址，然后在访问微程序控制存储器的情况下重写地址中的数据来防止错误的再生。构成：控制存储器2由寄存器6指定的地址读出并由ECC电路3检查。当检测到1位错误时，校正的数据被发送到寄存器4，如果不可校正的2位错误检测电路7打开门8，并将由寄存器6指定的控制存储器2产生的错误的地址存储在跟踪存储器9中。当从检测电路7发送错误信号时算术电路5通过端子A将信号报告给上位装置并启动加载电路1.然后算术电路5读出跟踪存储器9，向加载器电路1通知产生的错误的地址，并重写在地址中更正数据。因此，容易地进行重写，并且可以防止错误的再生。

46. 发明专利

JPS5860353A LOGICAL OPERATION CIRCUIT 失效
公开(公告)号：JPS5860353A
公开(公告)日：1983-04-09
申请号：JP15900381
申请日：1981-10-06
申请人： FUJITSU LTD
发明人： TANIYAMA YUKIO
IPC分类号： G06F11/10 , G06F7/00
摘要： PURPOSE:To attain the automatic correction of a logical operation circuit with the comparatively low capacity of hardware by preparating forecasting check bits for the logical operation circuit and comparing the forecasting ckeck bits with that prepared from actual logical operation results. CONSTITUTION:Receiving an output of a logical operation circuit 11 executing AND, OR, EOR, and ADD operation and a bus signal, check bit generating circuits 12a-12f add check bits using Hamming codes to respective input data. Forecasting check bits are prepared through an EOR gate and an OR gate in accordance with said added check bits and the kinds of operation. A circuit 12f compares check bits prepared from the output data of real operation results with forecasting check bits and outputs syndrome patterns S0-S4 for error correction. An error check circuit 13 corrects the output data of the circuit 11 by the syndrome patterns and outputs corrected data.

47. 发明专利

JPS5827249A CONTROL CIRCUIT FOR MULTIPLEXED ARITHMETIC AND LOGIC UNIT 失效
公开(公告)号：JPS5827249A
公开(公告)日：1983-02-17
申请号：JP12458481
申请日：1981-08-08
申请人： FUJITSU LTD
发明人： TANIYAMA YUKIO , WADA TADAHIRO
IPC分类号： G06F11/20 , G06F11/16
摘要： PURPOSE:To continue the execution of a microprocessor by using the outputs of a normal multiplex device and to prevent a titled circuit from the regeneration of errors by comparing outputs of the multiplexing device to demarcate faults. CONSTITUTION:Data from registers 1, 2 are inputted to arithmetic and logic units (ALU) 31, 32 and outputs from respective units are inputted to a comparator 4 and an output switching circuit 5, respectively. A collated result is outputted from the comparator 4 and, if the result is normal, a control circuit 6 is actuated and the output switching circuit 5 adop an output from one previously fixed unit, the ALU31 or ALU32, and sends the output to a data bus D-BUS. When a fault is detected by the comparator 4, a diagnosing means is executed by an output signal from a starting circuit 7 and either of the normal units, ALU31 or ALU32, is discriminated. The control circuit 6 actuates the output switching circuit 5 by said discriminated signal and sends an output result form the normal ALU31 or ALU32 to the D-BUS.

48. 发明专利

JPS5692626A INPUT*OUTPUT CONTROL SYSTEM 失效
公开(公告)号：JPS5692626A
公开(公告)日：1981-07-27
申请号：JP16989579
申请日：1979-12-26
申请人： FUJITSU LTD
发明人： TANIYAMA YUKIO , NAGABORI TETSUO
IPC分类号： G06F13/10 , G06F3/00
摘要： PURPOSE:To reduce the instruction start time of input/output control device, by scanning and referring the inquiry memory before the end of operation of I/O is informed to CPU, and providing the means to store the content when inquiry is made. CONSTITUTION:A scanning circuit II12 is started with a machine cycle and signal, and the input of a multiplexer MPX3, i.e., the scanning of the content of an inquiry memory 1 is made before the information of CPU. As a result, if at least one inquiry state is present in the memory 1, FF15 is set and the presence of inquiry is stored. Thus, an AND gate 9 is closed and the input and output start instruction is waited. After that, FF8 is set with the scanning end signal I of a scanning circuit I11, FF15 is reset with the output Q, the gate 9 is opened, the machine cycle start signal is formed, and the machine cycle start circuit 10 is started. If no inquiry is made, FF15 is not set, the output Q of FF8 is 0, the gate 9 is opened, the I/O controller is immediately operated and the instruction start time is reduced.

49. 发明专利

JPS55129953A SLIP CHECK SYSTEM IN MAGNETIC TAPE DEVICE 失效
公开(公告)号：JPS55129953A
公开(公告)日：1980-10-08
申请号：JP3683379
申请日：1979-03-30
申请人： FUJITSU LTD
发明人： TANIYAMA YUKIO , WADA TADAHIRO
IPC分类号： G11B15/28
摘要： PURPOSE:To perform slip check more exactly by starting write modulation when the speed does not reach a fixed value and by comparing tachometer pulses at this time with data pulses. CONSTITUTION:The output of tachometer 5 is counted as tachometer pulse intervals by tachometer pulse sensor 6 and the second counter 7, and the first and the second speeds are detected by speed detection means 9. When speed detection means 9 detects the first speed Va, modulating circuit 11 starts to start write. When written data reaches read head 4, the output is stored in register 15 through peak detector 13, etc. Meanwhile, the third counter 10 counts pulses only during the passage time of the tape through the head gap on the basis of the output of the second speed Vb and stops. Then, the output of the third counter 10 is applied to comparator circuit 21 together with data pulses through counter 14 and is compared with the reference value for no slip to detect slip. Thus, more exact check is possible.

50. 发明专利

JPS5588144A REGISTER SELECTIVE DIAGNOSTIC SYSTEM 失效
公开(公告)号：JPS5588144A
公开(公告)日：1980-07-03
申请号：JP15997678
申请日：1978-12-27
申请人： FUJITSU LTD
发明人： TANIYAMA YUKIO , ISAKA TETSUO
IPC分类号： G06F11/22 , G06F11/00
摘要： PURPOSE:To find an error securely by transferring a specific output bit of a register selected by a selective signal direct to a processor requesting its content and then by checking the selective signal by a microprogram. CONSTITUTION:When an error code is outputted to a fixed field of a microinstruction, an operation signal is applied to register address register 21, which reads an address of error register 10 to be selected indicated by the instruction, and decoder 12 decodes it to output a register selective signal to line 13. This selective signal opens AND circuits 11a-11g and respective bit outputs of register 10 are applied to OR circits 14a-14g. Outputs of those circuits 14a-14g and that of OR circuit 15 are supplied to arithmetic circuit 17 via bus 16 and circuit 17 applies each information to an arithmetic register, so that a microprogram wil diagnose an error of each bit.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式