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    • 36. 发明专利
    • PLL FREQUENCY SYNTHESIZER
    • JPH0730413A
    • 1995-01-31
    • JP17142793
    • 1993-07-12
    • NEC CORP
    • NAGAKURA TOMIO
    • H03L7/10H03L3/00H03L7/187H03L7/189
    • PURPOSE:To provide a frequency synthesizer capable of stably executing high speed frequency pull-in independently of the existence of a temperature change or device dispersion. CONSTITUTION:A control part 10 stores information relating to the frequency control voltage of a voltage controlled oscillator 5 and device status temperature from a temperature detecting circuit 13 in a storage part 12 at the time of stabilizing frequency. When the device is restarted, the control part 10 reads out these information from the storage part 12, reads out the voltage change value of a voltage change corresponding to a current temperature change from a ROM 14 and sends a synthetic digital signal obtained by synthesizing respective voltage values to a D/A converter 11. The D/A converter 11 converts the synthetic digital signal and outputs a compensated analog signal compensated at its temperature. Since the output voltage of the compensated analog signal is impressed to a loop filter 8, prescribed frequency is set up in the oscillator 5 through the loop filter 8 when the device is restarted.
    • 37. 发明专利
    • PHASE LOCKED LOOP FREQUENCY SYNTHESIZER
    • JPH06152405A
    • 1994-05-31
    • JP32381092
    • 1992-11-10
    • MITSUBISHI ELECTRIC CORP
    • ANDO AKIRA
    • H03L7/089H03L7/107H03L7/187H03L7/189H03L7/199
    • PURPOSE:To reduce error at the time of frequency switching and to shorten frequency pull-in time by switching the frequency dividing ratios of reference and comparative frequency dividers and performing initial phase matching by reset. CONSTITUTION:A control voltage VL provided through a first loop filter F1 is charged/discharged to the capacitor 110 of another second loop filter F2 by a voltage follower 118. Thus, the same frequency is kept even after switches 107 and 104 are changed over to the side of '0' by a switch changeover signal FLTSW. At the same time, the control voltage of a frequency fine adjustment terminal Q is changed, and a transmission frequency is shifted downward. Consequently, the voltage of a frequency control terminal P at a voltage controlled oscillator(VCO) 101 does not change but matches the lower side just by the component of shifting the transmission frequency. Then, a switch 122 is turned on by a switch changeover signal PDTSW, a loop is closed, comparative and reference frequency dividers 102 and 104 are reset by a reset signal DIVRST from a controller 120, and initial phases are matched. Thus, frequency disturbance on a second stage can be suppressed.