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31. 发明专利

JP2006032888A Semiconductor device and manufacturing method for semiconductor device 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：JP2006032888A
公开(公告)日：2006-02-02
申请号：JP2004334629
申请日：2004-11-18
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： IKEDA YASUSHI , OKAMOTO MASAHIDE , HARUTA AKIRA , KAGII HIDEMASA , OKA HIROTAKE , NAKAMURA HIROYUKI
IPC分类号： H01L21/52 , H01L21/60 , H01L23/495
CPC分类号： H01L23/49562 , H01L23/49513 , H01L23/49524 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L2224/04026 , H01L2224/05111 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05644 , H01L2224/2908 , H01L2224/29083 , H01L2224/29101 , H01L2224/29109 , H01L2224/29111 , H01L2224/29118 , H01L2224/29123 , H01L2224/29124 , H01L2224/29139 , H01L2224/29147 , H01L2224/29155 , H01L2224/2919 , H01L2224/32013 , H01L2224/32057 , H01L2224/32245 , H01L2224/32507 , H01L2224/37147 , H01L2224/40095 , H01L2224/40247 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48644 , H01L2224/48699 , H01L2224/73265 , H01L2224/83191 , H01L2224/83192 , H01L2224/83801 , H01L2224/83805 , H01L2224/84801 , H01L2224/85205 , H01L2224/92247 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01063 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/01327 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13055 , H01L2924/15747 , H01L2924/15787 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/01032 , H01L2924/00012 , H01L2924/01022 , H01L2924/01026 , H01L2924/01083 , H01L2924/3512 , H01L2224/48744 , H01L2924/00015 , H01L2224/83205
摘要： PROBLEM TO BE SOLVED: To provide a power semiconductor device where a power semiconductor element is die-mount-connected on a lead frame free from lead(Pb). SOLUTION: In the die-mount-connection of the power semiconductor element 1a and the lead frame 2 whose difference between thermal expansion coefficients of them is large, the connection is carried out with a inter-metal compound layer having a melting point of ≥260°C or with a solder of 260°C to 400°C free from Pb, and relaxing thermal stress generated through a temperature cycle by a metal layer having a melting point of 260°C or higher. The free Pb die-mount-connection which is not melted in reflow and does not generate a chip crack caused by the thermal stress can be carried out. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种功率半导体器件，其中功率半导体元件管芯安装在不含铅（Pb）的引线框架上。解决方案：在功率半导体元件1a和引线框架2的热膨胀系数差大的引线框架2的管芯安装连接中，用具有熔点的金属间化合物层进行连接 ≥260℃的焊料或者不含铅的260℃〜400℃的焊料，通过熔点为260℃以上的金属层通过温度循环产生的松弛热应力。可以进行在回流中不熔融并且不产生由热应力引起的芯片裂纹的自由Pb模具安装连接。版权所有（C）2006，JPO＆NCIPI

32. 发明专利

JP2005310907A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005310907A
公开(公告)日：2005-11-04
申请号：JP2004123153
申请日：2004-04-19
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： UNO TOMOAKI , SHIRAISHI MASAKI , MATSUURA NOBUYOSHI , NAGASAWA TOSHIO
IPC分类号： H01L25/07 , H01L21/8238 , H01L25/04 , H01L25/18 , H01L27/092 , H01L29/06 , H01L29/78 , H02M1/08 , H02M3/155 , H02M7/217
CPC分类号： H02M1/08 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/0603 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40137 , H01L2224/40245 , H01L2224/40247 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2224/49175 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2224/8485 , H01L2224/85444 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01059 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2924/20753
摘要： PROBLEM TO BE SOLVED: To improve voltage conversion efficiency in a semiconductor device constituting a DC/DC converter. SOLUTION: The non-insulated DC/DC converter is provided with a circuit, in which a power MOS FET for high-side switch and a power MOS FET for low-side switch are connected in series. The power MOS FET for high-side switch, the power MOS FET for low-side switch, a driver circuit for controlling their operation, and a Schottky barrier diode connected in parallel with the power MOS FET for low-side switch, are respectively formed in different semiconductor chips 5a to 5d; and the four semiconductor chips 5a to 5d are housed together in a single package 6. In this case, the semiconductor chips 5b and 5d are mounted on the same die pad 7a2. The semiconductor chips 5a and 5c are placed close to each other. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提高构成DC / DC转换器的半导体器件中的电压转换效率。解决方案：非绝缘DC / DC转换器配备有电路，其中用于高侧开关的功率MOS FET和用于低侧开关的功率MOS FET串联连接。分别形成用于高侧开关的功率MOS FET，用于低侧开关的功率MOS FET，用于控制其工作的驱动电路和与用于低侧开关的功率MOS FET并联连接的肖特基势垒二极管在不同的半导体芯片5a至5d中; 并且四个半导体芯片5a至5d一起容纳在单个封装6中。在这种情况下，半导体芯片5b和5d安装在相同的芯片焊盘7a2上。半导体芯片5a和5c彼此靠近放置。版权所有（C）2006，JPO＆NCIPI

33. 发明专利

JP2005243685A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005243685A
公开(公告)日：2005-09-08
申请号：JP2004047859
申请日：2004-02-24
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： NAMITA TOSHIYUKI
IPC分类号： H01L23/48
CPC分类号： H01L2224/32245 , H01L2224/37 , H01L2224/37147 , H01L2224/40 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/45124 , H01L2224/48247 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve the reliability of the connection of a lead to an electrode pad by using a connecting board. SOLUTION: A semiconductor device includes a seal; a support substrate from which at least a part is covered with the seal and a lower surface becomes a drain electrode exposed from the lower surface of the seal; a drain lead which is connected to the support substrate, and which projects from the one side face of the seal; a source lead and a gate lead which project from the one side face of the seal, and extend in alignment with the drain lead; a semiconductor chip having a source electrode pad and a gate electrode pad on the upper surface covered with the seal, and having a drain electrode on the lower surface and fixed at the lower surface to the upper surface of the support substrate through a conductive adhesive; the connecting board disposed in the seal and electrically connecting the source electrode pad to the source lead; and a wire disposed in the seal to connect the gate electrode pad to the gate lead. The connecting board is made of a metal plate having a thin part and a thick part and having a flat upper surface. The lower surface of the thick part is adhered to the source electrode pad through a conductive adhesive. The lower surface of the thin part is adhered to the source lead through the conductive adhesive. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过使用连接板来提高引线与电极焊盘的连接的可靠性。解决方案：半导体器件包括密封件; 支撑基板，至少一部分由该密封件覆盖，下表面成为从密封件的下表面露出的漏电极; 漏极引线，其连接到所述支撑基板，并且从所述密封件的一个侧面突出; 源极引线和栅极引线，其从密封件的一个侧面突出并且与漏极引线对准延伸; 半导体芯片，具有覆盖有密封件的上表面的源电极焊盘和栅电极焊盘，并且在下表面具有漏电极，并通过导电粘合剂固定在支撑基板的上表面的下表面; 所述连接板设置在所述密封件中并将所述源电极焊盘电连接到所述源极引线; 以及设置在密封件中以将栅电极焊盘连接到栅极引线的导线。连接板由具有薄部分和较厚部分并具有平坦上表面的金属板制成。厚部分的下表面通过导电粘合剂粘附到源电极焊盘。薄部分的下表面通过导电粘合剂粘附到源极。版权所有（C）2005，JPO＆NCIPI

34. 发明专利

JP3637330B2 Semiconductor device 有权
公开(公告)号：JP3637330B2
公开(公告)日：2005-04-13
申请号：JP2002141495
申请日：2002-05-16
申请人：株式会社東芝
发明人：宏文松木 , 孝弘河野 , 彰夫高野
IPC分类号： H01L21/28 , H01L23/482 , H01L23/495 , H01L29/41 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L23/4824 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/49 , H01L29/41741 , H01L29/41766 , H01L29/4941 , H01L29/7802 , H01L2224/04042 , H01L2224/05552 , H01L2224/05624 , H01L2224/0603 , H01L2224/32245 , H01L2224/37124 , H01L2224/37147 , H01L2224/40091 , H01L2224/40245 , H01L2224/40247 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/4911 , H01L2224/73221 , H01L2224/73265 , H01L2224/84205 , H01L2924/00014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor device comprising a semiconductor substrate having first and second surfaces opposing each other, the substrate including a plurality of cells sharing a common drain region, each of the cells having source and gate regions, a surface source electrode connected to the source region of each of the cells and provided on the first surface, a strap member coupled with the surface source electrode by ultrasonic waves, a gate polysilicon wiring layer connecting the gate region of each of the cells and having a silicide layer in at least a portion of a surface thereof, a surface gate electrode connected to the gate polysilicon wiring layer and provided on the first surface, and a drain electrode provided on the second surface and shared by the cells.

35. 发明专利

JP2005011986A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005011986A
公开(公告)日：2005-01-13
申请号：JP2003174464
申请日：2003-06-19
申请人： Kanto Sanyo Semiconductors Co Ltd , Sanyo Electric Co Ltd , 三洋電機株式会社 , 関東三洋セミコンダクターズ株式会社
发明人： YOSHIBA SHIGEJI , FUKUDA HIROKAZU , SAKAI HARUHIKO
IPC分类号： H01L25/18 , H01L23/495 , H01L25/065 , H01L25/07 , H01L27/04 , H01L29/72 , H01L29/78
CPC分类号： H01L29/7813 , H01L23/49575 , H01L24/05 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/05624 , H01L2224/131 , H01L2224/13144 , H01L2224/16225 , H01L2224/16245 , H01L2224/32145 , H01L2224/371 , H01L2224/40095 , H01L2224/40225 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/73221 , H01L2224/73253 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12035 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To solve the following problems: the conventional one chip dual-type MOSFET has a structure of two MOSFET chips disposed with drain electrodes shorted to increase a packaging area and a resistance between the drain electrodes can not be decreased. SOLUTION: The drain electrodes of the two MOSFET semiconductor chips are directly connected and the two chips are overlapped. As it is unnecessary to draw the drain electrodes outside in the dual type MOSFET, only two gate terminals and two source terminals are needed to be drawn out, and these four terminals are drawn out by a lead frame or a conductive pattern. This realizes a downsizing and a low ON-resistance of the device. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了解决以下问题：传统的单芯片双型MOSFET具有两个MOSFET芯片的结构，漏极电极短路以增加封装面积，并且漏电极之间的电阻不能降低。解决方案：两个MOSFET半导体芯片的漏极直接连接，两个芯片重叠。由于不需要在双型MOSFET中将漏极电极吸引到外部，所以只需要两个栅极端子和两个源极端子，这四个端子由引线框架或导电图案引出。这实现了设备的小型化和低导通电阻。版权所有（C）2005，JPO＆NCIPI

36. 实用新型

JPS59155749U JPS59155749U - 失效
公开(公告)号：JPS59155749U
公开(公告)日：1984-10-19
申请号：JP5108883
申请日：1983-04-04
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L2224/40 , H01L2224/40247 , H01L2224/41 , H01L2224/4103 , H01L2924/00012

37. 发明专利

JPS5948947A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5948947A
公开(公告)日：1984-03-21
申请号：JP15887682
申请日：1982-09-14
申请人： Toshiba Corp
发明人： OONO TADAAKI , FUJII YOSHIMICHI
IPC分类号： H01L21/60 , H01L23/495
CPC分类号： H01L24/06 , H01L23/49541 , H01L23/49579 , H01L2224/04042 , H01L2224/40 , H01L2224/40091 , H01L2224/40247 , H01L2224/45 , H01L2224/45012 , H01L2224/45013 , H01L2224/45014 , H01L2224/45016 , H01L2224/45124 , H01L2224/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/49 , H01L2224/49111 , H01L2224/49175 , H01L2224/78 , H01L2224/78313 , H01L2224/85 , H01L2224/85205 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/013 , H01L2224/37099
摘要： PURPOSE:To obtain the excellent characteristics for a chip when a large current is applied by a method wherein a flat wire is joined together in the direction of thickness and the strength and junction area of the chip are increased. CONSTITUTION:A supersonic junction is performed on an Al-Si metal wire having rectangular section and other metal wires 11e and 11b. A wire and an electrode have a flat surface, they have a large contact area and they have also a strong adhesive strength. According to this constitution, an emitter electrode can be replaced with a flat wire, for example, working hours can be reduced, and the percentage of rejects and the percentage of troubles in a long lifetime test can also be reduced.
摘要翻译：目的：为了在通过扁平线在厚度方向上接合在一起并且芯片的强度和接合面积增加的方法施加大电流时获得芯片的优异特性。构成：在具有矩形截面和其它金属线11e和11b的Al-Si金属线上进行超音速接合。电线和电极具有平坦的表面，它们具有大的接触面积，并且还具有很强的粘合强度。根据这种结构，可以用扁平线代替发射电极，例如可以减少工作时间，并且还可以减少长时间试验中的废品率和故障百分比。

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