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31. 发明专利

JPS58169610A CONNECTION CONTROL SYSTEM OF INPUT AND OUTPUT DEVICE 失效
公开(公告)号：JPS58169610A
公开(公告)日：1983-10-06
申请号：JP5284982
申请日：1982-03-31
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU
IPC分类号： G06F13/38 , G06F13/12
摘要： PURPOSE:To support plural channels with the same transmission line and to realize an economical operation, by multiplexing the transmission on a series transmission line and at the same time allotting dynamically the channel corresponding to a high-speed transmission mode. CONSTITUTION:Channel interfaces 4-1 and 4-2 are provided to a remote station adaptor 3 and connected to channels 2-1 and 2-2 respectively. A multiplexing circuit 25 prevents one of channels 2-1 and 2-2 from shifting to a high-speed transmission mode when the other starts its working in the high-speed transmission mode. Input/output interfaces 19-1 and 19-2 are provided to a remote station adaptor 14 at the side of an input/output device 24. A buffer 18 as well as a buffer 6 are controlled by a multiplexing circuit 26 so as to be exclusive to the high-speed transmission mode.

32. 发明专利

JPS57157663A COMMUNICATION SYSTEM 失效
公开(公告)号：JPS57157663A
公开(公告)日：1982-09-29
申请号：JP4342081
申请日：1981-03-25
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU
IPC分类号： H04L12/437
摘要： PURPOSE:To reduce influence exerted to a system due to a fault of a terminal, by providing a branching device and a compounding device on each terminal, connecting a bus line like a loop, and also providing a switch in the loop. CONSTITUTION:Each terminal, that is, nodes 1-4 are connected by bus lines 12, 13. A signal inputted through the line 12 is transferred to a terminal apparatus 9 through a branching device 14. When receiving a data from the line 13, it is executed in the same way through a branching device 15. A data from the apparatus 9 is loaded on the lines 12, 13 through compounding devices 16, 17. One of the switches 10, 11 is usually turned off. In case when a cable has been disconnected, data communication can be executed continuously by turning on all the switches.

33. 发明专利

JPS5720836A TRANSMISSION SYSTEM OF CIRCUIT SETTING INFORMATION 失效
公开(公告)号：JPS5720836A
公开(公告)日：1982-02-03
申请号：JP9608180
申请日：1980-07-14
申请人： FUJITSU LTD
发明人： HANAZAWA AKIO , HIGUCHI TAIHOU , MUNAKATA AKIO , HIWATARI AKITO
IPC分类号： H04L29/04 , G06F13/00 , G06F13/12 , H04L29/06
摘要： PURPOSE:To realize the use of a console, etc. of a service processor, by transmitting the setting information to a circuit connecting device from the service processor with use of an existing service processor ring in a circuit setting information transmission system. CONSTITUTION:The set items are prepared at an installation frame for ICP of a service processor 2 to ensure the connection of an asynchronous MODEM and a synchronous MODEM as well as a selection between ST1 and ST2 plus a selection between full- and half-double communications. Then an alteration of setting is carried out by an indication of the operator, and this alteration is displayed at the display part of the processor 2. This setting information is transmitted to a circuit connecting device 6 from the processor 2 through a service processor ring 8 and a communication control processor 3 during the loading of initial microprogram of the whole system or of only the processor 3. As a result, the console, display part, etc. of the service processor can be used.

34. 发明专利

JPS56137595A SHIFT REGISTER 失效
公开(公告)号：JPS56137595A
公开(公告)日：1981-10-27
申请号：JP4084480
申请日：1980-03-28
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU
IPC分类号： G11C19/00
摘要： PURPOSE:To enable to form the feedback type shift register which can take 2 of different states with 2 clocks, by giving a suitable input to the shift registers of n-stage. CONSTITUTION:Taking the status variables of each stage of shift registers in n- bit as X0, X1,-Xn-1, the input function of the feedback type shift register is expressed in formula (1). In the shift register like this, the function g(X0, X1-Xn-1) is determined so that 2 sets of state which n-stage of shift register can take can be connected entirely. For example, in a feedback type shift register formed with flip- flops D2-D0, the set is made to satisfy the above condition. Thus, the feedback type shift register in which 2 states can be taken with 2 clocks, can be formed.

35. 发明专利

JPS5610762A CIRCUIT SCANNING SYSTEM FOR COMMUNICATION CONTROL DEVICE 失效
公开(公告)号：JPS5610762A
公开(公告)日：1981-02-03
申请号：JP8571079
申请日：1979-07-06
申请人： FUJITSU LTD
发明人： HANAZAWA AKIO , HIWATARI AKITO , HIGUCHI TAIHOU
IPC分类号： H04L29/04 , G06F13/00 , H04L12/00
摘要： PURPOSE:To ensure an effective control for the circuit scanning in response to the acceleration of the communication velocity, by giving modification to the contents of the address counter via the circuit connecting unit plus the circuit control unit and the circuit scanning sequence changing unit each and then giving the control to decide the circuit number. CONSTITUTION:Circuit scanning circuit part 7 and circuit connecting unit 2 include respectively address counters 8 and 8', circuit number control units 9 and 9' which perform the switching control of the circuit number mode, and circuit scanning sequence changing units 10 and 10' which set variably the circuit number. And the advancing lock is supplied to counter 8' of unit 2 from circuit part 7. At the same time, part 7 supplies the circuit number mode indicating information plus the circuit scanning sequence indicating information to unit 2. The control is given to unit 2 so that units 9 and 10' may modify the contents of counter 8' and then decide the circuit number. In this way, an effective control is secured for the circuit scanning in response to the acceleration of the communication velocity.

36. 发明专利

JPS568570A DIAGNOSTIC SYSTEM FOR LOGIC CIRCUIT 失效
公开(公告)号：JPS568570A
公开(公告)日：1981-01-28
申请号：JP8376679
申请日：1979-07-02
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU
IPC分类号： G01R31/28
摘要： PURPOSE:To increase the test efficiency by executing divided tests to a multi-input logic gate using a multistage shift register. CONSTITUTION:AND circuit A of 16 inputs consists of input logic gates G1-G4 to which each of divided portions A1-A4, A5-A8, A9-A12 and A13-A16 of inputs A1-A16 are supplied, control gates G5-G8 which transmit these outputs as they are based on the control signal or deliver them after converting them forcedly into the harmless outputs, and output logic gate G9 which receives the output of each control gate. Then shift register SR is provided to give the control to each gates G5-G8. And test data Si of the desired pattern is written serially into the SR based on clock input CP and when diagnosis input D becomes to ''1''. Thus bits S1-S4 are used for test of circuit A; while bits S5-Sn are used for other circuits respectively.

37. 发明专利

JPS55123256A SYNCHRONOUS DETECTION SYSTEM 失效
公开(公告)号：JPS55123256A
公开(公告)日：1980-09-22
申请号：JP3022579
申请日：1979-03-15
申请人： FUJITSU LTD
发明人： HANAZAWA AKIO , SUGIZAKI HARUO , HIGUCHI TAIHOU
IPC分类号： H04L29/14 , G06F13/42 , H04L7/00
摘要： PURPOSE:To make it possible to detect rapidly an abnormal state without deteriorating the data processing performance of a communication controller and also to perform cutting operation in a short time by providing a circuit which detects the abnormal state in parallel to synchronous test operation. CONSTITUTION:When the state of receiving circuit R changes from ''1'' to ''0'' at time t0 and the state of indication circuit I also changes from OFF to ON, an abnormal state of circuit cutting indication is considered to have occurred. Then, this state is immediately detected to change the state of control circuit C from ON to OFF, and the state of transmitting circuit T is also changed from ''1'' to ''0'' to complete response operation (t1-t0) of incoming disconnection in a short time (within 100ms). Namely, before a synchronous character or start flag is tested by synchronous test circuit 27, the generation of eight continuous bits of ''0'' is detected by ''0'' detection circuit 28 to send interruption signal INT to a main control part and a control program starts fixed corresponding operation, thereby detecting the abnormal state.

38. 发明专利

JPS5531341A AUTOMATIC TEST PROCESSING METHOD 失效
公开(公告)号：JPS5531341A
公开(公告)日：1980-03-05
申请号：JP10461978
申请日：1978-08-28
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU , HANAZAWA AKIO , HIWATARI AKITO , NAGASE JIYUNICHI , NAKATSUKA MASAHIRO
IPC分类号： H04L29/04 , G06F13/00 , H04L12/26 , H04L29/14
摘要： PURPOSE:To save the trouble for the control of the packing state and the repairs of the parameter by carrying out a test after giving the sequential designation to each line set packaged from the circuit scanning part, deciding the types of the line setting types and then deciding the parameter of the test contents based on the decision result. CONSTITUTION:Line sets 1-0-1-7 are packed so as to secure the connection up to the maximum double 4 circuits, and the data transfer is carried out via circuit scanning part 3 and by the program control given by CPU4 and memory part 5. Here a test program is provided to give a test to the communication control unit, and line sets packed are given the sequential designation through part 3 to give a decision to the types of line sets. And based on the decision result, the test contents parameter is decided in accordance to each line set of the test program to perform a test. As a result, the operator can control the packing state, thus omitting the trouble for the repair of the parameter.

39. 发明专利

JPS60205765A TROUBLE DATA HOLDING SYSTEM 失效
公开(公告)号：JPS60205765A
公开(公告)日：1985-10-17
申请号：JP6393384
申请日：1984-03-30
申请人： FUJITSU LTD
发明人： CHIBA HIDEAKI , HIGUCHI TAIHOU , NAKAMURA TAKASHI
IPC分类号： H04L29/14 , G06F13/00 , H04L13/00
摘要： PURPOSE:To hold and take out line information data by providing a write inhibition control bit and a mode designating bit in a control area where line information data is stored, and using both bits to inhibit rewrite when a trouble occurs in a line. CONSTITUTION:When an input/output instruction execution cycle L concerning a line N is taken, a control part 19 is commanded to set a bit WIH to ''1'' by a write pulse, and a bit MOD is reset to ''0''. When the content of a control area 12n are read out to start a character processing execution cycle N, a trouble is detected by parity check or the like. If a trouble is generated, a write inhibition condition generating circuit 17 outputs the output, and an AND circuit 22 outputs an output STMOD if the bit WIH is set simultaneously. A bus BUS1 between a read register 15 and a write circuit 16 is opened to store the content of the control area 12n in the read register 15 again in the control area 12n in a control area storage memory 11 together with the bit WIH.

40. 发明专利

JPS6061854A CONNECTION SYSTEM AMONG CIRCUIT BLOCKS 失效
公开(公告)号：JPS6061854A
公开(公告)日：1985-04-09
申请号：JP16859583
申请日：1983-09-13
申请人： FUJITSU LTD
发明人： CHIBA HIDEAKI , HIGUCHI TAIHOU , HANAZAWA AKIO
IPC分类号： H04L29/10 , G06F13/22 , G06F13/372
摘要： PURPOSE:To obtain a connection system of simple structure which facilitates the extension of a control and a controlled part by cascading plural control parts and controlled parts through a bus, and circulating a synchronizing signal and using the bus on time-division basis. CONSTITUTION:Line connection parts 41'-44' receive delay signals CTLI1- CTLI4 generated by passing the synchronizing signal CTL through a signal line 8 to read line address information on the bus 9, and identify whether the information is their own line addresses or not respectively. When so, the connection parts receive control data DOTL1-DOTL4 arriving next or control lines after internal arithmetic. Receive data from the lines are held at the line connection parts 41'-44' and then sent out as state data onto the bus synchronously with the delay signals CTLI1-CTLI4. The synchronizing signal CTLO returned to line scanning mechanisms 31'-33' from a common control part 6 through the line connection parts 41'-44' is delayed by passing through the signal line 8 become timing signals CTLR1-CTLR3, which are timing signals for allowing the line scanning mechanisms 31'-33' to receive state data DIN1-DIN3 from the bus.

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