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31. 发明专利

JPH04133153A ADDRESS CONVERSION SYSTEM 失效
公开(公告)号：JPH04133153A
公开(公告)日：1992-05-07
申请号：JP25613590
申请日：1990-09-26
申请人： NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD
发明人： MASUDA ETSUO , UEMORI AKIRA , NAMIKAWA IKUO , KIMURA MINORU
IPC分类号： G06F12/10 , G06F12/08 , G06F13/36
摘要： PURPOSE:To efficiently use the system bus by providing a bus converting circuit for converting an address format of a high system bus of a CPU side, discriminating a data transfer unit and a control space address, and executing an access to peripheral controller being a subordinate of a low system bus. CONSTITUTION:A bus converting circuit 10 is provided between a low system bus 30 for containing a peripheral controller, and a high system bus 20 for connecting a CPU, a main storage device, etc. The bus 20 is that which has a control space address of 32 bits, and the bus 30 is a standard bus. The CPU constitutes an address on the but 30 to an address format allocated to a different area at every data transfer unit and sends it out. The bus converting circuit 10 discriminates the data transfer unit and the control space address on the bus 30 from the address constituted in accordance with the address format, and executes an access to the peripheral controller.

32. 发明专利

JPH03241453A START-UP CONTROL SYSTEM FOR MULTIPROCESSOR 失效
公开(公告)号：JPH03241453A
公开(公告)日：1991-10-28
申请号：JP3910290
申请日：1990-02-20
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MASUDA ETSUO , UEMORI AKIRA
IPC分类号： G06F15/16 , G06F9/52 , G06F15/177
摘要： PURPOSE:To eliminate the need for the lock of a common bus for access contention in start-up sequence from plural CPUs and to suppress influence on the performance of a system by managing vacancy and filling information at every control register group, and converting a start-up origin CPU number to a corresponding register group number. CONSTITUTION:The pairs of control registers for start-up control less than the number of CPUs are provided in a device 10 started up by the CPUs 1000-100n-1 for data channel, etc., and a vacant register group capture control part which manages the vacancy and filling information at every control register group is provided. Also, a data channel device 101 converts the start-up original CPU number into the corresponding register group number, and make access a register of specific specification by control register specification information. In such a way, it is possible to evade the lock on the common bus 3 in the access contention from the plural CPUs1000-100n-1, and to suppress the influence on the performance of the system.

33. 发明专利

JPH03130864A START CONTROL SYSTEM FOR MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPH03130864A
公开(公告)日：1991-06-04
申请号：JP26996189
申请日：1989-10-17
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MASUDA ETSUO , WAKIMURA YOSHIAKI , KOMACHIYA TADAYOSHI
IPC分类号： G06F13/12 , G06F15/16 , G06F15/177
摘要： PURPOSE:To prevent the conflict of accesses among CPUs by providing the circuits at the CPU side and the side of a device to be started to transmit or receive the controller CPU number and the control register address and giving an access instruction to a control register from the CPU which controls the start of the device to be started. CONSTITUTION:The control registers are multiplexly for each type in number equal to (m) pieces of CPU 100 and receive accesses from these CPUs. In an input/output controller. Then one of those registers is selected and undergoes an access based on an outgoing ID (starting CPU number) informed from the starting CPU. Thus it is not required to perform a test to check whether another CPU is already started and controlled or not and to carry out a setting process. Furthermore the program of each CPU is not required to be conscious of the difference of plural control registers. Then no conflict of accesses is produced among CPUs.

34. 发明专利

JPH0380353A INTERRUPTION PROCESSING METHOD AND DATA CHANNEL DEVICE 失效
公开(公告)号：JPH0380353A
公开(公告)日：1991-04-05
申请号：JP21831989
申请日：1989-08-24
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MASUDA ETSUO , WAKIMURA YOSHIAKI , KOMACHIYA TADAYOSHI
IPC分类号： G06F13/12
摘要： PURPOSE:To release the problem of a conventional detecting delay by securing a constitution where the software nips even other interruption requests produced at a CH interruption when a CPU detects an interruption in a certain look-in cycle. CONSTITUTION:When a data channel device CH 101 gives the interruption factors received from the input/output IO layers 1040 - 104n-1 periodically and en bloc to a CPU 100 as the interruption flags, the channel state words CSW corresponding to the IO devices having the interruptions are successively read out. Then the interruption request flags are reset. Thus plural interruptions can be informed with a single interruption given from the CH 101. As a result, the software nips even other interruption requests produced at a CH interruption when the CPU 100 detects an interruption in a certain look-in cycle. As a result, the problem of a conventional detecting delay, etc., can be released.

35. 发明专利

JPH01258156A METHOD AND CIRCUIT FOR MEMORY ERROR PROCESSING 失效
公开(公告)号：JPH01258156A
公开(公告)日：1989-10-16
申请号：JP8527288
申请日：1988-04-08
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： FUTAGAMI ARATA , MASUDA ETSUO
IPC分类号： G06F12/16
摘要： PURPOSE:To improve the reliability of the whole of a memory device and to prevent the degradation in throughput by providing a register were a syndrome is stored, a circuit which compares the value of the syndrome for the just preceding read operation with that for the current read operation, and some control circuits to quickly decide a fixed trouble of memory error. CONSTITUTION:A means 2 where the syndrome is stored and a syndrome comparing means 3 are provided, and the means 3 compares the value of the syndrome for the current read operation with that for the just preceding read operation when error is detected by an error detecting means 1. That is, the value of the syndrome at the time of error detection and that for the just preceding read operation are compared; and when they coincide with each other, error is decided as a fixed trouble of the whole of a memory element and is processed because of the same error occurrence position in the read of continuous data from a memory 8. Thus, the efficient memory error processing of high reliability is performed for the fixed trouble of the whole of the memory element and partial fixed trouble and interrupted trouble in the memory element.

36. 发明专利

JPS56121138A BUFFER MEMORY CONTROLLING SYSTEM 失效
公开(公告)号：JPS56121138A
公开(公告)日：1981-09-22
申请号：JP2436980
申请日：1980-02-28
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： MASUDA ETSUO , NAKAMURA YUKIO , DOI AKIHIKO , FUJITA HIROSHI , HOSOKAWA CHIKAYOSHI
IPC分类号： H04L29/02 , G06F5/06 , G06F7/78 , G06F12/02 , G06F13/00
摘要： PURPOSE:To make it possible to efficiently accomodate and process all kinds of and a lot of different speed circuit terminals, by supervising idle data cells in the buffer area in common and in the lump as to all the circuit terminals, and dynamically controlling the assignment of the idle data cells. CONSTITUTION:After initializing, the data units I37-III39 are inputted from the circuit terminal #i. Data 37-39 are connected with a chain to the idle data cells which have been taken out in order from the idle data cell queue by the input controlling part, and are stored. The data cells 40-42, 43-46, 47-48 correspond to the units I-III, respectively. In this way, a data which has been stored in the buffer area is output to the outside of the memory, after processing. As a result, the data cell becomes idle, is released from the chain connected by the input/output controlling part, and if is added after the end cell of the queue of the idle cell. And, the pointer of the control area is updated by being accompanied by release of the data cell and addition to its idle data cell queue.

37. 发明专利

JPS56108157A DATA PROCESSOR 失效
公开(公告)号：JPS56108157A
公开(公告)日：1981-08-27
申请号：JP881480
申请日：1980-01-30
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： IKUTA AKIRA , MASUDA ETSUO , FUTAGAWA TAKESHI , DOI AKIHIKO , KIMURA AKIO
IPC分类号： G06F12/06 , G06F13/16 , G06F13/28
摘要： PURPOSE:To use an address bus of 8 bits with a CC in common, by isolating successively a 16-bit address given from the DMAC-LSI into a 8-bit row address and a 8-bit line address each for access. CONSTITUTION:The CC, DMAC-LSI and MM have the common memory address bus AB of 8 bits; and the CC, MM and IOC have the common data bus DB. The 16-bit address information given from the DMAC-LSI is first isolated into a row address of 8 bits by the MUX, and a row access is given to the MM through the AB. Then the address information is isolated into a line address of 8 bits, and an access is given to the MM via the AB. The CC sends the address of 8 bits to the MM via the AB to give the row access and then the line access. Thus the address given from the DAMC-LSI is performed by the address bus common to the CC, and accordingly the hardwares is reduced conveniently.

38. 发明专利

JP2003174474A COMMUNICATION SYSTEM BETWEEN SIGNAL DEVICES 审中-公开
公开(公告)号：JP2003174474A
公开(公告)日：2003-06-20
申请号：JP2001373910
申请日：2001-12-07
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： OGAWA TAKESHI , MASUDA ETSUO , MIZUNO SHIRO
IPC分类号： H04L12/807 , H04L12/811 , H04L12/931 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a communication system between signal devices via an ATMSW in which an AAL connection is not released even when traffic is concentrated on the out line of the ATMSW and congestion occurs. SOLUTION: A cell speed controller (6) is provided between a signal device (1) and an ATMSW (5), and a system managing device (9) is provided for controlling the relevant cell speed controller. When the congestion occurs on the out line of the ATMSW (5), the ATMSW transmits congestion occurrence information to the system managing device, and the system managing device controls the cell speed controller to selectively decelerate the speed of a signal routed to the out line where the congestion occurs. Otherwise, the system managing device (9) monitors the cell discard rate of the ATMSW and when it exceeds a prescribed threshold, the cell speed controller is controlled so as to selectively decelerate the speed of the signal routed to the out line where the congestion occurs. COPYRIGHT: (C)2003,JPO

39. 发明专利

JP2002215415A FAULT-TOLERANT SYSTEM AND FAULT SEPARATION METHOD THEREFOR 失效
公开(公告)号：JP2002215415A
公开(公告)日：2002-08-02
申请号：JP2001006338
申请日：2001-01-15
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MISHIMA TAKESHI , MASUDA ETSUO
IPC分类号： G06F11/18
摘要： PROBLEM TO BE SOLVED: To provide a fault-tolerant system capable of shortening the service interrupting time as much as possible by specifying a failed information processor in a short time in a duplication system, and to provide a fault separation method therefor. SOLUTION: Two information processors 10 and 20 and a collating device 30 respectively and sequentially generate the same information for fault detection and the collating device 30 compares three pieces of information for fault detection. Thereby, a fault occurrence is detected and an information processor where the fault has occurred is specified.

40. 发明专利

JP2002135330A INTER-NODE CONTROL SYSTEM 失效
公开(公告)号：JP2002135330A
公开(公告)日：2002-05-10
申请号：JP2001038867
申请日：2001-02-15
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TAKATANI NAOKI , MASUDA ETSUO
IPC分类号： H04L12/911 , H04L12/707 , H04L12/711 , H04L12/801 , H04L12/913 , H04L12/917 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide an inter-node control system that warrants a bandwidth of control communication in the case of the control communication between node units using an IP network and sets the bandwidth used for the control communication between the node units depending on the processing state. SOLUTION: The inter-node control system warrants the bandwidth between the node units MGC and MG making communication in the IP network, periodically transmits a monitor packet by return and changes the setting of the communication bandwidth between the node units when a mean value of delay times exceeds a preset threshold value.

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