专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明专利

JPH03147595A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH03147595A
公开(公告)日：1991-06-24
申请号：JP28298689
申请日：1989-11-01
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G11C11/416 , G11C11/41
摘要： PURPOSE:To reduce the area of a memory cell and to execute the high integration of a memory by providing the memory cell for supplying a positive or negative cell current to a bit line in accordance with storage information, when the memory cell is connected to one piece of bit line, and a word line is in a selection level. CONSTITUTION:The memory is provided with memory cells MC11, MC12, MC21 and MC22 which are connected to a bit line and supply a positive or negative cell current ICELL to the bit line in accordance with storage information, when at least the bit line is selected, and means BD1, BD2 for supplying a constant- current IR to the bit line. Also, the memory is provided with a sense amplifier SA for comparing whether a current (ICELL + IR) flowing to the selected bit line is larger or smaller than IR, and reading out the storage information. In such a manner, since only one piece of bit line is necessary for each cell, the area of the memory cell can be reduced, and the memory can be brought to high integration by that portion.

32. 发明专利

JPH0397246A SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JPH0397246A
公开(公告)日：1991-04-23
申请号：JP23282589
申请日：1989-09-11
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： H01L21/82 , H01L27/10
摘要： PURPOSE:To manufacture a semiconductor memory having a defect curing circuit by a method wherein programable elements are programmed in non- conductive state in the beginning and later in conductive state. CONSTITUTION:Fuses F1-F4, F51-F54 are programmed in non-conductive state in the beginning and later in conductive state. When all fuses F1-F4, F51-F54 are in the conductive state, e.g. in case A=1, B=1; C1=1, C2=0, C3=0, C4=0, C5=0, either one out of C1-C4 becomes 1 corresponding to the address signals A, B while C5 constantly becomes 0. At this time, the alteration of the fuses F1, F52, F54 into conductive state will suffice for the replacement of any defective word line driven by C1 with the space word line driven by C5. Through these procedures, when A=1, B=1, C1 becomes 0 to allow C5 to become 1. That is, the defect can be cured.

33. 发明专利

JPH0223594A BIPOLAR RAM 失效
公开(公告)号：JPH0223594A
公开(公告)日：1990-01-25
申请号：JP17095288
申请日：1988-07-11
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , OHATA KENICHI
IPC分类号： G11C11/411 , G11C11/40 , H01L21/8229 , H01L27/10 , H01L27/102
摘要： PURPOSE:To correct the fluctuation of the characteristic value of a load element in a memory cell with an information reading-out current by constituting the load of a constant-current circuit which supplies the information reading-out current to the memory cell to a prescribed state. CONSTITUTION:An electric current is supplied from a constant-current source circuits I1 and I2, each of which is composed of a diode D1, transistor (TR) Q3, and load 3, to an FF type bipolar RAM memory cell MC incorporating 1st and 2nd TRs Q1 and Q2 and loads Z1 and Z2. Supposing the load Z3 has the same constitution as the loads Z1 and Z2, or is a dummy memory cell having a constitution similar to the memory cell MC, fluctuation of the loads 1 and Z2 can be compensated by a reading-out current and the information reading-out voltage of the cell MC becomes constant. Therefore, the operation margin of the memory cell MC can be expanded.

34. 发明专利

JPS63168033A BIPOLAR MEMORY 失效
公开(公告)号：JPS63168033A
公开(公告)日：1988-07-12
申请号：JP31312886
申请日：1986-12-29
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OHATA KENICHI , YAMAGUCHI KUNIHIKO , HONMA NORIYUKI , KANETANI KAZUO , MATSUMOTO MASAAKI , NANBU HIROAKI
IPC分类号： H01L21/82 , G11C11/34 , G11C11/401 , G11C29/00 , G11C29/04 , H01L27/10
摘要： PURPOSE:To make memory circuits with redundancy suitable for bipolar memories by a method wherein the bases of emitter followers driving word lines are connected to fuses and clamp circuits. CONSTITUTION:Bipolar memories in respective lines of a memory main body 103 are driven through the intermediary of word lines 110 selected by emitter followers 11 the bases of which are connected to low clamp circuits 12 and defective bit cutting off fuses 102. The fuses 102 can be miniaturized by flowing smaller current of 1/(current amplification degree) than that of word lines 110 due to the bipolar memories driven through the intermediary of emitter follower 11. Furthermore, when the fuses 102 are cut off by deflective bit, the potential of defective word line 110 can be clamped down on no-selective potential by the circuits 12 not to saturate a transistor feeding the bipolar memories with constant current so that any defective insulation from bipolar circuits may be prevented from occurring to make memory circuits with redundancy suitable for the bipolar memories.

35. 发明专利

JPS63122100A BIPOLAR MEMORY 失效
公开(公告)号：JPS63122100A
公开(公告)日：1988-05-26
申请号：JP26765586
申请日：1986-11-12
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , OHATA KENICHI
IPC分类号： G11C11/413 , G06F12/16 , G11C11/34 , G11C29/00 , G11C29/42 , H01L21/8229 , H01L27/10 , H01L27/102
摘要： PURPOSE:To incorporate an error correcting function by storing horizontal and vertical parities of an input data in a memory at the time of the inputting of the data, comparing the parities with those of an output data at the time of outputting, and correcting an error. CONSTITUTION:A data inputted from data input terminals DI1-DI4 are stored in a memory cell array MA1, and at the same time, the parities against the input data generated by a parity generating circuit P1 are stored in a memory cell array MA2. To output data from the data output terminals DI1-DI4 of the array MA1, the parity generated by the parity generating circuit P2 and that stored in the array MA2 are compared with each other by a comparator C and by the result of the comparison, an error data is corrected by a correction circuit DCB, and thus the data are outputted to output terminals DO1-DO4. Accordingly, the error correction can be executed almost without increasing an access time.

36. 发明专利

JPS6383998A BIPOLAR RAM 失效
公开(公告)号：JPS6383998A
公开(公告)日：1988-04-14
申请号：JP22818886
申请日：1986-09-29
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , OHATA KENICHI
IPC分类号： G11C11/413 , G11C11/34 , G11C29/00 , G11C29/42
摘要： PURPOSE:To detect whether output data is error data corrupted with alpha rays, noise, or the like or not and highly integrate a RAM by comparing the parity, which the second parity generating circuit generates, with the parity which is stored in the second memory cell array and is generated by the first parity generating circuit. CONSTITUTION:At the time of data input, the parity for n-bit input data which a first parity generating circuit P1 is stored in the second memory cell array MA2. At the time of data output, it is discriminated by a comparing circuit C whether the parity for n-bit output data which the second parity generating circuit P2 and the parity which is stored in the second memory cell array MA2 and is generated by a first parity generating circuit P1 coincide with each other or not. Then, it is detected whether output data are error data corrupted with alpha rays, noise, or the like or not. Only one memory cell for parity storage is required for n-bit data in this case, and the chip area is extended only about (n+1)/n times if the storage capacity of a RAM is equalized to that of the conventional RAM, and the RAM is highly integrated well.

37. 发明专利

JPS62125662A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS62125662A
公开(公告)日：1987-06-06
申请号：JP26489685
申请日：1985-11-27
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KANETANI KAZUO , YAMAGUCHI KUNIHIKO , HONMA NORIYUKI , MATSUMOTO MASAAKI , NANBU HIROAKI , TANI KAZUHIKO , OHATA KENICHI
IPC分类号： H01L27/10 , G11C11/40 , G11C11/41
摘要： PURPOSE:To stabilize reducing and reading operations of a voltage drop by providing current supplying circuits for supplying operating currents of memory cells to driving lines at least at both ends of the driving lines. CONSTITUTION:Current supplying circuits 1A, 1B for supplying reading currents IRA, IRB to digit lines D11, D12-Dn1, Dn2 are provided at both ends of the digit lines. Voltages are presented at the lines D11, D12 in response to the contents of stored information of selected memory cells, detected by sensors SA, sense output signals SG, -SG are fed to an output circuit DO, which outputs a storage output Dout. The values of the currents IRA, IRB from the supplying circuits provided at both ends of the digit lines are set to 1/2 of the conventional current values to reduce the voltage drop due to wiring resistances of the digit lines to 1/2 of the conventional value. Thus, since a reduction in a voltage margin represented by a potential difference between the digit line voltage and a reference voltage of the sensor can be reduced, the operation of the sensor can be stabilized.

38. 发明专利

JPS62125598A DEFECT RELIEVING CIRCUIT 失效
公开(公告)号：JPS62125598A
公开(公告)日：1987-06-06
申请号：JP26489785
申请日：1985-11-27
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MATSUMOTO MASAAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , NANBU HIROAKI , TANI KAZUHIKO , OHATA KENICHI
IPC分类号： H01L27/10 , G11C11/34 , G11C11/413 , G11C29/00 , G11C29/04
摘要： PURPOSE:To secure a normal memory action just with one sense circuit by setting all normal word lines under the non-selection states when an address signal which selects a defective memory cell is produced and at the same time selecting one of spare word lines. CONSTITUTION:When the address signal of a defective memory cell is produced, a positive pulse is applied to a node N7 and then supplied to a node N2 via a transistor TrQ8. This voltage is higher than the reference voltage of a node N3 and therefore the current of a current source I11 flows to a TrQ4I (I=1-m) and then to a resistance R11 via a TrQ11. Thus the outputs of a decoder are all set at a low level of voltage at the node N1I. While the word lines are set under non-selection states. At the same time, the positive pulse voltage is applied also to a TrQ61 and the current of a current source I21 is switched to the TrQ61 form a TrQ71. Thus a node P11 is set at a high level of voltage and spare word lines are set under selection states. Thus it is possible to secure a normal memory action just with one sense circuit.

39. 发明专利

JPS6246498A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS6246498A
公开(公告)日：1987-02-28
申请号：JP18424185
申请日：1985-08-23
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OHATA KENICHI , YAMAGUCHI KUNIHIKO , HONMA NORIYUKI , KANETANI KAZUO , MATSUMOTO MASAAKI , NANBU HIROAKI , TANI KAZUHIKO
IPC分类号： G11C29/00 , G11C29/04
摘要： PURPOSE:To easily and effectively attain the high integration of a semiconductor memory having a redundancy without simply selecting a defective bit by breaking the electrical connection of a base of an emitter follower of a main memory drive circuit. CONSTITUTION:The line of a main memory cell array 14 through an X decoder 11 according to an X address signal is selected by an emitter follower 18. To the base of this emitter follower, a fuse 17 is connected and the fuse is disconnected to a defective line and the electrical connection of the emitter follower is disconnected and in place of the line, a preliminary line 15 is selected by a preliminary decoder 13. According to this constitution, an address comparison circuit or PROM or the like of a defective bit memory are not required, a chip area is reduced, a consumped power is lowered and a semiconductor memory having a redundancy can be easily and effectively highly integrated.

40. 发明专利

JPH11250669A SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH11250669A
公开(公告)日：1999-09-17
申请号：JP4648398
申请日：1998-02-27
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KUSUNOKI TAKESHI , OHATA KENICHI , ARAKAWA FUMIHIKO , NANBU HIROAKI , KANETANI KAZUO , YAMAZAKI SU , HIGETA KEIICHI , NISHIYAMA MASAHIKO
IPC分类号： G11C11/413
摘要： PROBLEM TO BE SOLVED: To reduce a chip occupying area by a circuit configuration for giving a voltage from a test external terminal to a memory cell at the time of screening by giving an output voltage from an internal power source voltage generator to the cell in a normal operating time state. SOLUTION: An external terminal VEXT directly led from a power source supply line VCM of a memory cell out of a chip is provided. And, an internal power source voltage generator VCMG has a function of an output terminal OUT to a high impedance state. Thus, an insertion of a MOS switch in series between the power source supply line of the cell, the internal power source voltage generator and a testing external terminal is not required. No voltage drop occurs at the switch. And, a chip occupying area of the circuit for giving an operating power to the cell can be reduced.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式