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31. 发明专利

JPH03229451A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03229451A
公开(公告)日：1991-10-11
申请号：JP2475290
申请日：1990-02-02
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： CHICHII MIKIO , OKAZAKI TAKAO
IPC分类号： H01L25/00 , H01L25/16 , H01L31/04
摘要： PURPOSE:To reduce a whole packaging area by mounting an article electrically connected to a semiconductor circuit device on the surface or the interior of a single package in which at least one semiconductor circuit device is encapsulated. CONSTITUTION:A semiconductor integrated circuit 30 is connected to a plurality of bonding wires 40 and is provided in a package 10, and photovoltaic cell 50 is fixed onto a principal surface of the package 10 in the state where it is exposed to the outside, using a desired adhesive and is connected to a power supply terminal 20a for supplying operation power to the semiconductor integrated circuit device 30 among a plurality of external connection terminals 20 through a printed wiring structure 60. The operation power of the semiconductor integrated circuit device 30 is supplied with power generated in the photovoltaic cell 50 by irradiating the photovoltaic cell 50 with external light 70. Thus, a package area is sharply reduced, compared with a case where the semiconductor integrated circuit device 30 and the photovoltaic cell 50 are mounted separately on desired packaging board.

32. 发明专利

JPS6473824A PLL CIRCUIT 失效
公开(公告)号：JPS6473824A
公开(公告)日：1989-03-20
申请号：JP22954587
申请日：1987-09-16
申请人： HITACHI LTD
发明人： OKAZAKI TAKAO , ENDO TAKEFUMI
IPC分类号： H03L7/093 , H03L7/08
摘要： PURPOSE:To reduce jitter due to a noise in a PLL circuit, by transmitting the noise superposed on a source voltage to the gate of a MOSFET which constitutes respective power source via a corresponding capacitor in an AC way. CONSTITUTION:P-channel MOSFETs Q1 and Q2 are provided in a series form between an output node and the source voltage Vcc of a circuit, and N-channel MOSFETs Q21 and Q22 are provided in the series form between the output node and the ground potential of the circuit. The capacitor C2 is provided between the gate of the MOSFETQ1 and the source voltage Vcc of the circuit, and the capacitor C3 is provided between the gate of the MOSFETQ22 and the ground potential of the circuit. In such a way, it is possible to suppress the fluctuation of the voltage between the gate and the source due to the noise and to obtain a comparatively stable discharge current.

33. 发明专利

JPS6352517A PLL CIRCUIT 失效
公开(公告)号：JPS6352517A
公开(公告)日：1988-03-05
申请号：JP19531886
申请日：1986-08-22
申请人： HITACHI LTD
发明人： OKAZAKI TAKAO , DAIMON KAZUO
IPC分类号： H03L7/10 , H03L7/107
摘要： PURPOSE:To decrease the pull in time at the start of operation and to prevent the increase in jitter by decreasing a high frequency gain, increasing a capacitance of a loop filter and decreasing a current of a current source for charge/ discharge after a prescribed time elapses from the start of phase control. CONSTITUTION:An output signal S of a timer circuit TM is fed to a current changeover circuit and also to the loop filter LPF. Until a prescribed time elapses from the start of the phase control of a PLL circuit, the output signal S of the circuit TM is at a low level, the high frequency gain of the PLL circuit is increased, and after a prescribed time elapses, the output signal S goes to a high level, the high frequency gain of the PLL circuit is decreased, MOSFETs Q8, Q9 of the LPF are turned on, and a capacitor C2 having a comparatively larger capacitance is connected to an output code and an output terminal of the LPF. Moreover, MOSFET Q3 or Q4 is turned on in this case, a charging current source IS3 and a discharge current source IS4 having a comparatively smaller current is connected to the output node and the output terminal of the LPF.

34. 发明专利

JP2011109423A High breakdown voltage switch circuit and semiconductor integrated circuit device employing the same 审中-公开
标题翻译：高断开电压开关电路和半导体集成电路装置
公开(公告)号：JP2011109423A
公开(公告)日：2011-06-02
申请号：JP2009262449
申请日：2009-11-18
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAYAMA AKIRA , ITO ATSUSHI , YOSHINAGA MAKI , OKAZAKI TAKAO
IPC分类号： H03K17/08 , H01L21/8234 , H01L27/088 , H03K17/687
摘要： PROBLEM TO BE SOLVED: To provide a bidirectional switch including a means for controlling a gate-source voltage of the bidirectional switch based on a drain voltage or a drain-source voltage in the bidirectional switch, and a switch driver for applying a voltage to a gate terminal of the switch via the control means.
SOLUTION: The bidirectional switch includes: a main switch which is a bidirectional switch; a means for controlling a gate-source voltage of the main switch based on a drain voltage and a source voltage of the main switch; and a switch driver for applying a voltage to a gate terminal of the main switch via the control means.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种双向开关，其包括用于基于双向开关中的漏极电压或漏极 - 源极电压来控制双向开关的栅极 - 源极电压的装置，以及用于施加双向开关的开关驱动器经由控制装置对开关的栅极端子施加电压。
解决方案：双向开关包括：作为双向开关的主开关; 用于基于所述主开关的漏极电压和源极电压来控制所述主开关的栅极 - 源极电压的装置; 以及用于经由控制装置向主开关的栅极端子施加电压的开关驱动器。版权所有（C）2011，JPO＆INPIT

35. 发明专利

JP2003045992A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2003045992A
公开(公告)日：2003-02-14
申请号：JP2002164556
申请日：2002-06-05
申请人： Eastern Japan Semiconductor Technologies Inc , Hitachi Ltd , 株式会社日立製作所 , 株式会社東日本セミコンダクタテクノロジ−ズ
发明人： TANBA HIROKO , HASE AKIHIRO , OKAZAKI TAKAO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device contriving high reliability.
SOLUTION: In the semiconductor integrated circuit supplying operation voltage from a plurality of independent power source supply terminals respectively and having interface transmitting a signal, gate breakage of input MOSFET of an interface part can be prevented by an electrostatic breakage prevention circuit even when high voltage is applied on each power source terminal due to static electricity in handling or the like of the semiconductor integrated circuit device by providing an electrostatic breakage prevention circuit costing of MOSFET connected by resistance and a diode to an interface part for transmitting a signal between electronic circuits.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供具有高可靠性的半导体集成电路器件。解决方案：在半导体集成电路中，分别从多个独立的电源端子提供工作电压并且具有传输信号的接口，即使高电压是通过静电破坏电路也可以防止接口部分的输入MOSFET的栅极断裂通过提供由电阻连接的MOSFET的成本的静电破坏电路和用于在电子电路之间传输信号的接口部分的二极管，由于在半导体集成电路器件的处理等中的静电而施加在每个电源端子上。

36. 发明专利

JP2000183748A OVER-SAMPLING A/D CONVERTER 失效
公开(公告)号：JP2000183748A
公开(公告)日：2000-06-30
申请号：JP35243198
申请日：1998-12-11
申请人： HITACHI LTD
发明人： OKAZAKI TAKAO
IPC分类号： H03M1/08 , H03M3/02
摘要： PROBLEM TO BE SOLVED: To enhance the S/N characteristic of a conventional over-sampling A/D converter adopting the ΔΣmodulation system. SOLUTION: The over-sampling A/D converter adopting the ΔΣmodulation system is provided with an analog differential amplifier circuit 30 that amplifiers a differential output of a modulation means 20 having a differential integration means 24 and outputs signals not being differential signals and with a voltage comparison means 40 that compares output voltages of the analog differential amplifier circuit 30 with a plurality of reference voltages. A local D/A converter 50 converts a signal in a plurality of bits obtained from the voltage comparison means 40 into an analog signal, which is fed back to modulation means 10, 20.

37. 发明专利

JPH11274895A Signal processing circuit and subscriber's circuit 失效
标题翻译：信号处理电路和订户电路
公开(公告)号：JPH11274895A
公开(公告)日：1999-10-08
申请号：JP7518398
申请日：1998-03-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ABE YOSHITAKA , OKAZAKI TAKAO
IPC分类号： H03H17/02 , H04Q3/42
摘要： PROBLEM TO BE SOLVED: To easily compensate the process variation of elements by outputting a coefficient in response to the process variation of the elements constituting an analog filter selectively to a digital filter from a filter coefficient table.
SOLUTION: In order to absorb the variation of resistors and capacitors, a filter coefficient switching means (SEL) 7 is provided to switch the filter coefficients of digital filters DFIL 1 to 4 by SEL 7. This switching is executed by transmitting a control signal to a filter coefficient table 6 through a control line 8 from SEL 7. Namely, by selectively switching from the combinations of digital filter coefficients prepared in advance, variation in a signal processing circuit is easily compensated. Thus, characteristic with respect to the variation of a semiconductor manufacturing process is improved.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：为了通过从滤波器系数表选择性地将数字滤波器的构成模块的滤波器的处理变化作为响应，输出系数来容易地补偿元件的工艺变化。解决方案：为了吸收电阻和电容的变化，提供了一个滤波器系数切换装置（SEL）7，用于通过SEL7来切换数字滤波器DFIL 1至4的滤波器系数。该切换是通过将控制信号发送到通过来自SEL7的控制线8的滤波器系数表6.即，通过从预先准备的数字滤波器系数的组合中选择性地切换，容易地补偿信号处理电路的变化。因此，提高了关于半导体制造工艺的变化的特性。

38. 发明专利

JPH1188923A SUBSCRIBER LINE SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH1188923A
公开(公告)日：1999-03-30
申请号：JP26788997
申请日：1997-09-12
申请人： HITACHI LTD
发明人： ABE YOSHITAKA , OKAZAKI TAKAO
IPC分类号： H03H17/00 , H03H17/02 , H04Q3/42
摘要： PROBLEM TO BE SOLVED: To provide the subscriber line signal processing circuit that is simplified. SOLUTION: An A/D converter circuit 2 of this processing circuit samples a received analog signal by a 1st sampling frequency and converts the analog signal into a digital signal, the output digital signal is given to a decimation filter 3, where the frequency is converted into a 2nd sampling frequency, output data of the decimation filter 3 are given to an interpolation filter 5. The frequency of the data is converted into a 3rd sampling frequency by the filter 5 and the output data are converted into an analog signal at a D/A converter circuit 6. In this case, an impedance filter 4 consisting of a series circuit comprising a FIR filter having a lead phase characteristic to compensate the lagged phase in the decimation filter 3 and the interpolation filter 5 and comprising an IIR filter realizing a desired frequency characteristic is provided between the output of the decimation filter 3 and the input to the interpolation filter 5.

39. 发明专利

JPH10242865A D/A CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH10242865A
公开(公告)日：1998-09-11
申请号：JP4520597
申请日：1997-02-28
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： OKAZAKI TAKAO , ABE YOSHITAKA , KITA MASAHITO , HASE AKIHIRO
IPC分类号： H03M1/08 , H03M1/66 , H03M3/04
摘要： PROBLEM TO BE SOLVED: To provide a D/A converter capable of improving the S/N characteristic. SOLUTION: This D/A converter is constituted of switch circuits U1-Un, D1-Dn which selectively extract a positive divided voltage output and a negative divided voltage output from a resistor circuit according to an amplitude selection signal and a differential amplifier 50 that differentially amplifies the positive divided voltage output and the negative divided voltage output extracted by the switch circuits. The positive divided voltage output and the negative divided voltage output around a reference voltage with respect to one of quantization outputs in a plurality of bits are produced from the resistor circuit 41 and they are differentially amplified to generate a specified analog voltage signal, then the S/N of the D/A converter is improved through the reducing action of a common mode noise component by the differential amplification.

40. 发明专利

JPH08316798A COMPARATOR 失效
公开(公告)号：JPH08316798A
公开(公告)日：1996-11-29
申请号：JP12264495
申请日：1995-05-22
申请人： HITACHI LTD
发明人： NAGAI TOMOKAZU , ABE YOSHITAKA , OKAZAKI TAKAO
IPC分类号： G01R19/165 , H03K3/0233 , H03K3/353 , H03K5/08
摘要： PURPOSE: To reduce the size of chip by forming two kinds of logic threshold levels at a kind of reference voltage so as to configure the comparator with a hysteresis characteristic through the changeover of an offset voltage generated in a differential amplifier circuit. CONSTITUTION: P-channel load transistors (TRs) M3 , M4 are connected to drains of differential MOS TRs M1 , M2 to form a current mirror circuit. When an input signal reaches an L level, a level of a control signal fed back to a control terminal 4 goes to an L level, a switch S1 is open and a switch S2 is closed to set a gate potential of a MOS TR M5 to aground potential. Thus, the TR M5 is nonconductive and only the TRs M1 , M2 connecting to a constant current source I0 conduct differential operation. When the Vin is set to H, the terminal 4 goes to an H level, the S1 is closed and the S2 is open and the TRs M1 , M2 , M5 conduct differential operation. Through the constitution above, a different offset voltage is generated in the differential amplifier circuit by turning on/off the TR M5 and two kinds of logic threshold levels are formed.

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