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    • 33. 发明专利
    • JPH05344006A
    • 1993-12-24
    • JP15206392
    • 1992-06-11
    • FUJITSU LTD
    • KAWASAKI TAKESHINISHI TETSUYAHAYAMI SHICHIROMUKAI HARUOKUROYANAGI TOMOJIHAJIKANO KAZUO
    • H03M13/00H04L1/00
    • PURPOSE:To simplify the circuit configuration by inputting directly an inputted code word to a remainder arithmetic operation means so as to use the circuit in common. CONSTITUTION:A remainder arithmetic operation means 1 calculates a residue of an input code word subjected to change through part of rewrite divided by a generation polynomial. An exclusive OR means 2 takes exclusive OR between a check bit in the changed input code and an output of the remainder arithmetic operation means 1. Then a selection means 3 uses an output of the exclusive OR means 2 as a new check bit of the changed input code word to generate a new code word. That is, a level '1' in the residue obtained in the output of the remainder arithmetic operation means 1 indicates that a check bit at a relevant location is changed through the part of rewrite and then the check bit of this location is inverted by the exclusive OR means 2 to obtain a new check bit. Thus, it is not required to make all of check bit parts of the inputted code word and a code word check section and a code word generating section are formed by a common circuit.