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    • 35. 发明专利
    • INTEGRATED CIRCUIT PROTECTIVE DEVICE
    • JPH10294425A
    • 1998-11-04
    • JP9998697
    • 1997-04-17
    • DENSO CORP
    • MATSUOKA TOSHIHIKOSHIOTANI TAKESHISUZUKI MASAHIRO
    • H01L27/04H01L21/822
    • PROBLEM TO BE SOLVED: To provide an integrated circuit protective device which can lower the voltage for operating a controlled rectifier element as a semiconductor integrated circuit protective element with the minimum circuit area. SOLUTION: SCRs(silicon-controlled rectifiers) 5 and 6 are incorporated in a protective device 1 connected to the input-output terminal 19 of an LSI (large scale integration) circuit 18 and the n-type layer 9 corresponding to the n-gate of the SCR 5 is connected to the power source 20 of the LSI circuit 18. The p-type layer 13 corresponding to the p-gate of the SCR 6 is connected to a grounding terminal through a resistor 21. When positive ESD(electrostatic discharge) is impressed upon the terminal 19 and the potential at the ESD is higher than the sum of the voltage at the power source 20 and the forward voltage at a p-n junction 22a, the SCR 5 conducts to discharge the ESD through the ground and, when negative ESD is impressed upon the terminal 19 and the potential at the ESD is negatively higher than the sum of the ground potential and the forward voltage at a p-n junction 25a, the SCR 6 conducts to discharge the ESD through the ground.
    • 36. 发明专利
    • SEMICONDUCTOR DEVICE
    • JP2002299617A
    • 2002-10-11
    • JP2001097174
    • 2001-03-29
    • DENSO CORP
    • SUZUKI MASAHIRO
    • H01L29/78
    • PROBLEM TO BE SOLVED: To provide a semiconductor device allowing equal current to flow through the upper part of a channel and the lower part of the channel in the semiconductor device having a channel the width of which is set to be in the depth direction of a substrate for making current flow in a direction parallel to the main surface of the substrate. SOLUTION: By using an n type substrate 1 having a main surface 1a and a backside 1b to be a surface opposite to the main surface 1a, a recess is formed from the side of the main surface 1a of the n type substrate 1. After that, a drift area 1c, a p type base region 2 and an n type source region 3 are embedded by using an epitaxial growth technique, power MOSFET is constituted. The impurity concentration of the respective regions and the regions of source, drain regions are designed, set and manufactured so that a resistance value at the depth direction of the source-drain regions (the thickness direction of the substrate 1) may be equal substantially.